參數(shù)資料
型號(hào): W78M32V100BI
英文描述: 8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package
中文描述: 8Mx32閃光3.3V的頁(yè)面模式同步讀/寫(xiě)操作多芯片封裝
文件頁(yè)數(shù): 35/54頁(yè)
文件大?。?/td> 756K
代理商: W78M32V100BI
35
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W78M32V-XBX
April 2006
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
TABLE 14. SECTOR PROTECTION COMMAND DEFINITIONS
Command (Notes)
C
Bus Cycles (Notes 1-4)
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Addr
Data
Addr
Data
Addr
Data
Reset
SecSi Sector Entry
SecSi Sector Exit
SecSi Protection
Bit Program (5, 6)
Sector Protection
Bit Status
Password
Program (5, 7, 8)
Password Verify
(6, 8, 9)
Password Unlock
(7, 10, 11)
PPB Program
(5, 6, 12)
PPB Status
All PPB Erase
(5, 6, 13, 14)
PPB Lock Bit Set
PPB Lock Bit
Status (15)
DYB Write (7)
DYB Erase (7)
DYB Status (6)
PPMLB Program
(5, 6, 12)
PPMLB Status (5)
SPMLB Program
(5, 6, 12)
SPMLB Status (5)
Legend:
DYB = Dynamic Protection Bit
OW = Address (A7:A0) is (00011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
1
3
4
6
XXX
555
555
555
F0
AA
AA
AA
2AA
2AA
2AA
55
55
55
555
555
555
88
90
60
XX
OW
00
68
OW
48
OW
RD (0)
5
555
AA
2AA
55
555
60
OW
48
OW
RD(0)
4
555
AA
2AA
55
555
38
XX[0-3]
PD[0-3]
4
555
AA
2AA
55
555
C8
PWA[0-3]
PWD[0-3]
7
555
AA
2AA
55
555
28
PWA[0]
PWD[0]
PWA[1]
PWD[1]
PWA[2]
PWD[2]
PWA[3]
PWD[3]
6
555
AA
2AA
55
555
60
(SA)WP
68
(SA)WP
48
(SA)WP
RD(0)
4
6
555
555
AA
AA
2AA
2AA
55
55
555
555
90
60
(SA)WP
WP
RD(0)
60
(SA)
40
(SA)WP
RD(0)
3
4
555
555
AA
AA
2AA
2AA
55
55
555
555
78
58
SA
RD(1)
4
4
4
6
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
48
48
58
60
SA
SA
SA
PL
X1
X0
48
68
PL
48
PL
RD(0)
5
6
555
555
AA
AA
2AA
2AA
55
55
555
555
60
60
PL
SL
48
68
PL
SL
RD(0)
48
SL
RD(0)
5
555
AA
2AA
55
555
60
SL
48
SL
RD(0)
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits
A22:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
8. Entire command sequence must be entered for each portion of password.
9. Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at addresses 0-3.
11. A 2 μs timeout is required between any two portions of password.
12. A 100 μs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when
DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again.
Before issuing erase command, all PPBs should be programmed to prevent PPB
overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
1. See
Table 1
for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as
shown in table, address bits higher than A11 (except where BA is required) and data
bits higher than DQ7 are don’t cares.
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been
fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be
issued and verified again.
7. Data is latched on the rising edge of WE#.
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