參數(shù)資料
型號(hào)： W78M32V90BI
英文描述： 8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package
中文描述： 8Mx32閃光3.3V的頁(yè)面模式同步讀/寫操作多芯片封裝
文件頁(yè)數(shù)： 4/54頁(yè)
文件大?。?/td> 756K
代理商： W78M32V90BI
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W78M32V-XBX
April 2006
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is a latch used to store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs
to the internal state machine. The state machine outputs
dictate the function of the device.
Table 1
lists the device
bus operations, the inputs and control levels they require,
and the resulting output. The following subsections describe
each of these operations in further detail.
TABLE 1. DEVICE BUS OPERATION
3
CS#
OE#
WE#
Operation
RESET#
WP#/ACC
Addresses
(A22-A0)
A
IN
A
IN
X
DQ15-DQ0
Read
Write
Standby
L
L
L
H
X
H
L
X
H
H
X
X
D
OUT
D
IN
High-Z
V
IO
±
0.3 V
L
X
X
V
IO
±
0.3 V
H
L
V
ID
X (Note 2)
Output Disable
Reset
Temporary Sector Unprotect (High
Voltage
Legend
: L = Logic Low = V
IL
, H = Logic High = V
IH,
V
ID
= 11.5-12.5 V, V
HH
= 8.5-9.5 V, X = Don’t Care, SA = Sector Address, A
IN
= Address In, D
IN
= Data In,
D
OUT
= Data Out
Notes
:
1.
The sector protect and sector unprotect functions may also be Implemented via programming equipment. See the High Voltage Sector Protection section.
2.
WP#/ACC must be high when writing to sectors 0, 1, 268, or 269.
3.
For each chip
H
X
X
H
X
X
X
X
X
X
X
High-Z
High-Z
D
IN
A
IN
REQUIREMENTS FOR READING
ARRAY DATA
To read array data from the outputs, the system must drive
the OE# and appropriate CS# pins to V
IL
. CS# is the power
control. OE# is the output control and gates array data to
the output pins. WE# should remain at V
IH.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device
address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until
the command register contents are altered.
Refer to the
AC Characteristics
table for timing specifications
and to Figure 11 for the timing diagram. I
CC1
in the
DC Characteristics table represents the active current
specification for reading array data.
Random Read (Non-Page Read)
Address access time (t
ACC
) is equal to the delay from stable
addresses to valid output data. The chip enable access
time (t
CS
) is the delay from the stable addresses and stable
CS# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE#
to valid data at the output inputs (assuming the addresses
have been stable for at least t
ACC
–t
OE
time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random
locations within a page. Address bits A22–A3 select an 8
word page, and address bits A2–A0 select a specific word
within that page. This is an asynchronous operation with the
microprocessor supplying the specific word location.
The random or initial page access is t
ACC
or t
CS
and
subsequent page read accesses (as long as the locations
specified by the microprocessor falls within that page) is
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