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參數(shù)資料
| 型號： | W78M64V-100SBM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 64 FLASH 3.3V PROM MODULE, 100 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 32/54頁 |
| 文件大?。?/td> | 1349K |
| 代理商： | W78M64V-100SBM |
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38
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64V-XSBX
July 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
DQ2: TOGGLE BIT II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether
that sector is erase-suspended. Toggle Bit II is valid after
the rising edge of the nal WE# pulse in the command
sequence.
DQ2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CS# to control the read
cycles.) But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison,
indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are required for
sector and mode information. Refer to Table 15 to compare
outputs for DQ2 and DQ6.
Figure 9 shows the toggle bit algorithm in owchart form, and
the section “DQ2: Toggle Bit II” explains the algorithm. See
also the DQ6: Toggle Bit I subsection. Figure 20 shows the
toggle bit timing diagram. Figure 21 shows the differences
between DQ2 and DQ6 in graphical form.
READING TOGGLE BITS DQ6/DQ2
Refer to Figure 9 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
DQ7–DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the rst read. After the
second read, the system would compare the new value of
the toggle bit with the rst. If the toggle bit is not toggling,
the device has completed the program or erase operation.
The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see
the section on DQ5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as DQ5 went
high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If
it is still toggling, the device did not completed the operation
successfully, and the system must write the reset command
to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and DQ5 has not gone high.
The system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when
it returns to determine the status of the operation (top of
Figure 9).
DQ5: EXCEEDED TIMING LIMITS
DQ5 indicates whether the program or erase time has
exceeded a specied internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to
program a “1” to a location that was previously programmed
to “0.” Only an erase operation can change a “0”
back to a “1.”
Under this condition, the device halts the
operation, and when the timing limit has been exceeded,
DQ5 produces a “1.”
Under both these conditions, the system must write the
reset command to return to the read mode (or to the erase-
suspend-read mode if a bank was previously in the erase-
suspend-program mode).
DQ3: SECTOR ERASE TIMER
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not erasure
has begun. (The sector erase timer does not apply to the
chip erase command.) If additional sectors are selected
for erasure, the entire time-out also applies after each
additional sector erase command. When the time-out period
is complete, DQ3 switches from a “0” to a “1.” See also the
Sector Erase Command Sequence section.
After the sector erase command is written, the system should
read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure that the device has accepted the command
sequence, and then read DQ3. If DQ3 is “1,” the Embedded
Erase algorithm has begun; all further commands (except
Erase Suspend) are ignored until the erase operation is
complete. If DQ3 is “0,” the device will accept additional
sector erase commands. To ensure the command has been
accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase
command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 15 shows the status of DQ3 relative to the other
status bits.
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