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參數(shù)資料
| 型號： | W78M64V-120SBC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 64 FLASH 3.3V PROM MODULE, 120 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 51/54頁 |
| 文件大小： | 1349K |
| 代理商： | W78M64V-120SBC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64V-XSBX
July 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
STANDBY MODE
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE#
input. The device enters the CMOS standby mode when the
CS# and RESET# pins are both held at VIO ± 0.3 V. If CS#
and RESET# are held at VIH, but not within VIO ± 0.3 V, the
device will be in the standby mode, but the standby current
will be greater. The device requires standard access time
(tCS) for read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics table represents the CMOS
standby current specication.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC + 150 ns. The
automatic sleep mode is independent of the CS#, WE#,
and OE# control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available
to the system. Note that during automatic sleep mode,
OE# must be at VIH before the device reduces current
to the stated sleep mode specication. ICC5 in the DC
Characteristics table represents the automatic sleep mode
current specication.
RESET#: HARDWARE RESET PIN
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin is
driven low for at least a period of tRP, the device immediately
terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration
of the RESET# pulse. The device also resets the internal
state machine to reading array data. The operation that
was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS±0.3 V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL but
not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up rmware from the
Flash memory.
If RESET# is asserted during a program or erase operation,
the RY/BY# pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time of tREADY (during
Embedded Algorithms). The system can thus monitor RY/
BY# to determine whether the reset operation is complete.
If RESET# is asserted when a program or erase operation
is not executing (RY/BY# pin is “1”), the reset operation is
completed within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the RESET#
pin returns to VIH.
Refer to theAC Characteristic tables for RESET# parameters
and to Figure 14 for the timing diagram.
OUTPUT DISABLE MODE
When the OE# input is at VIH, output from the device is
disabled. The output pins (except for RY/BY#) are placed
in the highest Impedance state.
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