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參數(shù)資料
| 型號(hào)： | W78M64V-70SBM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 64 FLASH 3.3V PROM MODULE, 70 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 31/54頁 |
| 文件大?。?/td> | 1349K |
| 代理商： | W78M64V-70SBM |
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37
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64V-XSBX
July 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
RY/BY#: READY/BUSY#
The RY/BY# is a dedicated, open-drain output pin which
indicates whether an Embedded Algorithm is in progress or
complete. The RY/BY# status is valid after the rising edge
of the nal WE# pulse in the command sequence. Since
RY/BY# is an open-drain output, several RY/BY# pins can
be tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
in the read mode, the standby mode, or one of the banks is
in the erase-suspend- read mode.
Table 15 shows the outputs for RY/BY#.
DQ6: TOGGLE BIT I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the nal WE# pulse in the command
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause DQ6 to
toggle. The system may use either OE# or CS# to control
the read cycles. When the operation is complete, DQ6
stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for
approximately 400 μs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the
device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7: Data#
Polling).
If a program address falls within a protected sector, DQ6
toggles for approximately 1 μs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm
is complete.
Table 15 shows the outputs for Toggle Bit I on DQ6.
Figure 9 shows the toggle bit algorithm. Figure 20 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 21 shows the differences between DQ2
and DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.
START
No
Yes
DQ5=1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Toggle Bit
= Toggle?
Read Byte Twice
(DQ7–DQ0)
Address = VA
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit
may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2
for more information.
FIGURE 9. TOGGLE BIT ALGORITHM
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