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參數資料
| 型號： | W89C92P |
| 英文描述： | 10M CMOS Coaxial Transceiver |
| 中文描述： | 1000萬的CMOS收發(fā)同軸 |
| 文件頁數： | 2/11頁 |
| 文件大?。?/td> | 169K |
| 代理商： | W89C92P |
W89C92
- 2 -
PIN DESCRIPTION
Attachment Unit Interface Pins
CSO+, CSO- (DIP 1, 2/PLCC 2, 3) (O/P): Collision Output Positive, Collision Output Negative
CSO+/CSO- are a differential signal pair that drives 10 MHz signals to the DTE (data transmit
equipment) when a collision is detected on the segment, the DTE transmits an excessively long
packet, or the cable is disconnected. CSO+/CSO- are also active for a period of time after the end of
every transmission. CSO+ and CSO- should be pulled down by a 510 ohm resistor.
DI+, DI- (DIP 3, 6/PLCC 4, 12) (O/P): Data-in Output Positive, Data-in Output Negative
DI+/DI- are also a differential signal pair. Signals received from the network segment that meet the
bandwidth requirement and carrier sense levels will be transferred into differential format and driven
out from DI+/DI-. A 510 ohm pull-down resistor is also required for DI+/DI-.
DO+, DO- (DIP 7, 8/PLCC 13, 14) (I/P): Data-out Input Positive, Data-out Input Negative
Data transmitted from the DTE are received on DO+/DO- and transferred into a current signal on the
coaxial cable.
Coaxial Media Interface Pins
TXO (DIP 15/PLCC 28) (O/P): Transmit Output
The current signal on the coaxial cable is sunk into TXO. TXO is pulled up to V
DD
internally. A diode
should be used to isolate the TXO capacitance loading from the coaxial cable.
RXI (DIP 14/PLCC 26) (I/P): Receive Input
The signal on RXI is filtered by a low-pass filter and transferred to DI+/DI- with differential format. The
RXI should be connected directly to the coaxial cable.
CLS (DIP 16/PLCC 1) (I/P): Collision Sense Input
The collision detection threshold is determined by the level of the CLS pin. The transmit mode
collision detection of 10BASE2 is implemented when CLS is connected directly to V
DD
.
Control Pins
ER+, ER- (DIP 11, 12/PLCC 18, 19) (I/P): External Resistor Positive, External Resistor Negative
A fixed 1K 1% ohm resistor should be connected between ER+ and ER- to establish the internal
operating current.
SQE (DIP 9/PLCC 15) (I/P): Signal Quality Error Test
The signal quality error test will be enabled when SQE is tied to V
DD
. The jabber lockup function can
be disabled by changing the SQE bias.
Power Pins
V
DD
(DIP 10/PLCC 16, 17) (I/P): Positive Power Supply
A9 VDC power supply is needed.
V
SS
(DIP 4, 5, 13/PLCC 5 to 11, 20 to 25) (I/P): Negative Power Supply
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