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參數(shù)資料
| 型號： | W9425G6JB-5 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封裝： | 8 X 13 MM, ROHS COMPLIANT, TFBGA-60 |
| 文件頁數(shù)： | 16/50頁 |
| 文件大小： | 852K |
| 代理商： | W9425G6JB-5 |
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W9425G6JB
Publication Release Date: Oct. 08, 2010
- 23 -
Revision A01
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
Voltage on I/O Pins Relative to VSS
VIN, VOUT
-0.5 ~ VDDQ +0.5
V
Voltage on Input Pins Relative to VSS
VIN
-1 ~ 3.6
V
Voltage on VDD Supply Relative to VSS
VDD
-1 ~ 3.6
V
Voltage on VDDQ Supply Relative to VSS
VDDQ
-1 ~ 3.6
V
Operating Temperature
TOPR
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 150
°C
Soldering Temperature (10s)
TSOLDER
260
°C
Power Dissipation
PD
1
W
Short Circuit Output Current
IOUT
50
mA
Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
9.2 Recommended DC Operating Conditions
(TA = 0 to 70°C)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
NOTES
VDD
Supply Voltage
2.3
2.5
2.7
V
2
VDDQ
Supply Voltage for I/O Buffer
2.3
2.5
2.7
V
2
VREF
Input reference Voltage
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2, 3
VTT
Termination Voltage (System)
VREF - 0.04
VREF
VREF + 0.04
V
2, 8
VIH (DC)
Input High Voltage (DC)
VREF + 0.15
-
VDDQ + 0.3
V
2
VIL (DC)
Input Low Voltage (DC)
-0.3
-
VREF - 0.15
V
2
VICK (DC)
Differential Clock DC Input Voltage
-0.3
-
VDDQ + 0.3
V
15
VID (DC)
Input Differential Voltage.
CLK and CLK inputs (DC)
0.36
-
VDDQ + 0.6
V
13, 15
VIH (AC)
Input High Voltage (AC)
VREF + 0.31
-
V
2
VIL (AC)
Input Low Voltage (AC)
-
VREF - 0.31
V
2
VID (AC)
Input Differential Voltage.
CLK and CLK inputs (AC)
0.7
-
VDDQ + 0.6
V
13, 15
VX (AC)
Differential AC input Cross Point
Voltage
VDDQ/2 - 0.2
-
VDDQ/2 + 0.2
V
12, 15
VISO (AC)
Differential Clock AC Middle Point
VDDQ/2 - 0.2
-
VDDQ/2 + 0.2
V
14, 15
Notes: Undershoot Limit: VIL (min) = -1.5V with a pulse width < 5 nS
Overshoot Limit: VIH (max) = VDDQ +1.5V with a pulse width < 5 nS
VIH (DC) and VIL (DC) are levels to maintain the current logic state.
VIH (AC) and VIL (AC) are levels to change to the new logic state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9425G6JB-5 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ |
| W9425G6JB-5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9425G6JB-5I TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR SDRAM X16, 200MHZ, IN |
| W9425G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4 M × 4 BANKS × 16 BITS DDR SDRAM |
| W9425G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 66-Pin TSOP-II 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY 制造商:Winbond 功能描述:16MX16,256MB DDR,250MHZ,2.5V , TSOP 66PIN GREEN |
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