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參數(shù)資料
| 型號： | W982504AH-8H |
| 英文描述： | x4 SDRAM |
| 中文描述： | x4內(nèi)存 |
| 文件頁數(shù)： | 12/41頁 |
| 文件大小： | 1369K |
| 代理商： | W982504AH-8H |
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W982504AH
- 12 -
read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write
operation, then any residual data from the burst write cycle will be ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2
.
Table 2 Address Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
BL = 2 (disturb address is A0)
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
No address carry from A0 to A1
BL = 4 (disturb addresses are A0 and A1)
No address carry from A1 to A2
BL = 8 (disturb addresses are A0, A1 and A2)
No address carry from A2 to A3
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
ACCESS ADDRESS
BUST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 4
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 8
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W982508AH-7 | x8 SDRAM |
| W982508AH-75 | x8 SDRAM |
| W982508AH-8H | x8 SDRAM |
| W982516AH-7 | x16 SDRAM |
| W982516AH-75 | x16 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W982508AH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M X 4 BANKS X 8 BIT SDRAM |
| W982508AH-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| W982508AH-75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| W982508AH-8H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| W982516AH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 4 BANKS x 16BIT SDRAM |
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