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參數(shù)資料
| 型號： | W982516AH-8H |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 3/41頁 |
| 文件大?。?/td> | 1369K |
| 代理商： | W982516AH-8H |
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W982504AH
Publication Release Date: December 2000
- 3 -
Revision A2
PIN DESCRIPTION
PIN NO.
PIN NAME
FUNCTION
DESCRIPTION
23
26, 22,
29
36
A0
A12
Address
Multiplexed pins for row and column address.
Row address: A0
A12. Column address: A0
A9, A11.
20, 21
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
5, 11, 44, 50 DQ0
DQ3
Data
Input/Output
Multiplexed pins for data output and input.
19
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is ignored
and previous operation continues.
18
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of the
clock, RAS , CAS and WE define the operation to be
executed.
17
CAS
Column
Address
Strobe
Referred to RAS
16
WE
Write Enable Referred to RAS
39
DQM
Input/Output
Mask
The output buffer is placed at Hi-Z(with latency of 2) when
DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with
zero latency.
38
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
37
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
1, 14, 27
V
CC
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
28, 41, 54
V
SS
Ground
Ground for input buffers and logic circuit inside DRAM.
3, 9, 43, 49
V
CC
Q
Power (+3.3V)
for I/O Buffer
Separated power from V
CC
, to improve DQ noise
immunity.
6, 12, 46, 52
V
SS
Q
Ground
for I/O Buffer
Separated ground from V
SS
, to improve DQ noise
immunity.
2, 4, 7, 8, 10,
13, 15, 40,
42, 45, 47,
48, 51, 53
NC
No Connection No connection
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