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參數(shù)資料
| 型號： | W986432DH-5 |
| 英文描述： | SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| 中文描述： | 內存| 4X512KX32 |的CMOS | TSSOP封裝| 86PIN |塑料 |
| 文件頁數(shù)： | 17/48頁 |
| 文件大?。?/td> | 1283K |
| 代理商： | W986432DH-5 |
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W986432DH
Publication Release Date: September 4, 2001
- 17 -
Revision A3
Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the
devices.
2. All voltages are referenced to V
SS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of t
CK
and t
RC
.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up Sequence
(1) Power up must be performed in the following sequence.
(2) Power must be applied to V
CC
and V
CCQ
(simultaneously) while all input signals are held in the “NOP” state. The CLK
signals must be started at the same time.
(3) After power-up a pause of at least 200 ìseconds is required. It is required that DQM and CKE signals then be held ‘
high‘(V
CC
levels) to ensure that the DQ output is impedance.
(4) All banks must be precharged.
(5) The Mode Register Set command must be asserted to initialize the Mode Register.
(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device.
6. AC Testing Conditions
PARAMETER
CONDITIONS
1.4V
See diagram below
2.4V/0.4V
1 nS
1.4V
Output Reference Level
Output Load
Input Signal Levels (V
IH
/V
IL
)
Transition Time (Rise and Fall) of Input Signal
Input Reference Level
50 ohms
1.4 V
AC TEST LOAD
Z = 50 ohms
output
30pF
1. Transition times are measured between V
IH
and V
IL
.
2. t
HZ
defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
3. These parameters account for the number of clock cycles and depend on the operating frequency of the clock,
as follows the number of clock cycles = specified value of timing/ clock period
(count fractions as whole number)
(1) t
CH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min.).
t
CL
is the pulse width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max.).
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相關代理商/技術參數(shù) |
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|---|---|
| W986432DH-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| W986432DH-6I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| W986432DH-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| W986432DH-7L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC |
| W9864G2DH6 | 制造商:WINBOND 功能描述:New |
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