
W9968CF
Publication Release Date: May 1999
- 13 - Revision A2
UV[7:0]
2-9
Digital UV (Chrominance) Inputs in 16-bit Mode, or Not Used in
8-bit Mode.
HS
116
Horizontal Sync Input. Programmable polarity.
VS
115
Vertical Sync Input. Programmable polarity.
VICLK
127
nput Video Clock.
SDE#/SDS
112
O
Serial Data Enable/Serial Data Strobe.
SCLK
113
B
Serial Interface Clock.
SDATA
114
B
Serial Interface Data.
Micro Controller Interface (21 pins)
Pin Name
Pin Number
Type
Description
AD[7:0]
21-24, 26-29
B
Multiplexed Address/Data Bus.
EXTMCU = 1:
High-order Address Bus.
EXTMCU = 0:
General Purpose I/Os.
A[15:8]
GPIO[7:0]
31-38
B
ALE
18
Address Latch Enable. ALE is used to enable the address latch
that separates the address from the data on AD bus.
RD#
15
U
Data Read Strobe.
WR#
16
U
Data Write Strobe.
EXTMCU = 1:
Chip Select.
EXTMCU = 0:
Snap Shot Input.
CS#
SANP#
17
U
NT#
14
O
nterrupt Output, level-triggered.
Serial E
2
PROM Interface (2 pins)
Pin Name
Pin Number
Type
Description
SCL
62
O
Serial Clock.
Serial Data/Serial E
2
PROM Detection. During a reset operation,
the W9968CF samples this signal to see if an external E
2
PROM
exists. A 10K ohm pull-up resistor should be used if an external
E
2
PROM is used; otherwise it should be tied to VSS.
SDA/EEPRO
M
63
B
Miscellaneous (11 pins)
Pin Name
Pin Number
Type
Description