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參數(shù)資料
| 型號： | WE128K32-300G2UQ |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 128K X 32 EEPROM 5V MODULE, 300 ns, CQFP68 |
| 封裝： | 22.40 MM, CERAMIC, LQFP-68 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 347K |
| 代理商： | WE128K32-300G2UQ |
4
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WE128K32-XXX
White Electronic Designs
WRITE
A write cycle is initiated when OE is high and a low
pulse is on WE or CS with CS or WE low. The
address is latched on the falling edge of CS or WE
whichever occurs last. The data is latched by the
rising edge of CS or WE, whichever occurs first. A
byte write operation will automatically continue to
completion.
WRITE CYCLE TIMING
Figures 5 and 6 show the write cycle timing relation-
ships. A write cycle begins with address application,
write enable and chip select. Chip select is accom-
plished by placing the CS line low. Write enable
consists of setting the WE line low. The write cycle
begins when the last of either CS or WE goes low.
The WE line transition from high to low also initiates
an internal 150 sec delay timer to permit page mode
operation. Each subsequent WE transition from high
to low that occurs before the completion of the 150
sec time out will restart the timer from zero. The
operation of the timer is the same as a retriggerable
one-shot.
AC WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
WriteCycleParameter
Symbol
Min
Max
Unit
Write Cycle Time, TYP = 6ms
tWC
10
ms
Address Set-upTime
tAS
0ns
Write Pulse Width (WE or CS)
tWP
150
ns
Chip Select Set-upTime
tCS
0ns
Address HoldTime
tAH
100
ns
Data HoldTime
tDH
10
ns
Chip Select HoldTime
tCSH
0ns
Data Set-upTime
tDS
100
ns
Output Enable Set-upTime
tOES
10
ns
Output Enable HoldTime
tOEH
10
ns
Write Pulse Width High
tWPH
50
ns
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