參數(shù)資料
型號: WE256K8-300CMA
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: PROM
英文描述: EEPROM 5V MODULE, CDIP32
封裝: CERAMIC, HERMETIC SEALED DIP-32
文件頁數(shù): 10/13頁
文件大?。?/td> 678K
代理商: WE256K8-300CMA
WE512K8, WE256K8,
WE128K8-XCX
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
March 2007
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specications without notice.
WRITE CYCLE TIMING
Figures 6 and 7 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE
line low. The write cycle begins when the last of either CS#
or WE# goes low.
The WE# line transition from high to low also initiates
an internal 150μsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150μsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
WRITE
Write operations are initiated when both CS# and WE#
are low and OE# is high. The EEPROM devices support
both a CS# and WE# controlled write cycle. The address is
latched by the falling edge of either CS# or WE#, whichever
occurs last.
The data is latched internally by the rising edge of either
CS# or WE#, whichever occurs rst. A byte write operation
will automatically continue to completion.
AC WRITE CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
512K x 8
256K x 8
128K x 8
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time, TYP = 6mS
tWC
10
ms
Address Set-up Time
tAS
10
30
ns
Write Pulse Width (WE# or CS#)
tWP
150
ns
Chip Select Set-up Time
tCS
000
ns
Address Hold Time (1)
tAH
125
50
ns
Data Hold Time
tDH
10
0
ns
Chip Select Hold Time
tCH
000
ns
Data Set-up Time
tDS
100
ns
Output Enable Set-up Time
tOES
10
30
ns
Output Enable Hold Time
tOEH
10
0
ns
Write Pulse Width High
tWPH
50
ns
NOTES:
1. A17 and A18 must remain valid through WE# and CS# low pulse, for 512K x 8.
A15, A16, and A17 must remain valid through WE# and CS# low pulse, for 256K x 8.
A15 and A16 must remain valid through WE# and CS# low pulse, for 128K x 8.
相關(guān)PDF資料
PDF描述
W3H64M72E-533ESM 64M X 72 DDR DRAM, 0.5 ns, PBGA208
WPS256K16T-20LJI 256K X 16 STANDARD SRAM, 20 ns, PDSO44
WMF256K8-70FEI5 256K X 8 FLASH 5V PROM, 70 ns, CDFP32
WMF256K8-70DEC5A 256K X 8 FLASH 5V PROM, 70 ns, CDSO32
WMF256K8-90DEM5 256K X 8 FLASH 5V PROM, 90 ns, CDSO32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
WE256K8-300CQ 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx8 CMOS EEPROM, WE512K8-XCX, SMD 5962-93091
WE256K8-300CQA 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx8 CMOS EEPROM, WE512K8-XCX, SMD 5962-93091
WE256K8-XCX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM MCP
WE25M40 制造商:Hotpoint 功能描述:BEARING KIT 制造商:HOTPOINT 功能描述:BEARING KIT
WE278 制造商:Carlo Gavazzi 功能描述: