
6
White Microelectronics Phoenix, AZ (602) 437-1520
10
EEPROM
MODULES
FIG. 6
PAGE WRITE CYCLE
NOTES:
1. Between successive byte writes within page write operation, OE can be
strobed Low: e.g. this can be done with CS and WE High to fetch data from
another memory device within the system for the next write; or within WE
High and CS Low effectively performing a polling operation.
2. The timings shown above are unique to page write operations. Individual
byte load operations within the page write must conform to either the CS or
WE controlled write cycle timing.
OE (1)
CS
WE
ADDRESS (2)
DATA
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n + 1
LAST BYTE
tWC
t WPH
tWP
tBLC
WE32K32-XXX
PAGE WRITE OPERATION
The WE32K32-XXX has a page write operation that allows one to
128 bytes of data to be written into the device and consecutively
loads during the internal programming period. Successive bytes
may be loaded in the same manner after the first data byte has
been loaded. An internal timer begins a time out operation at each
write cycle. If another write cycle is completed within 100
s or
less, a new time out period begins. Each write cycle restarts the
delay period. The write cycles can be continued as long as the
interval is less than the time out period.
The usual procedure is to increment the least significant
address lines from A0 through A5 at each write cycle. In this
manner a page of up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning the relatively long
interval programming cycle.
After the 100
s time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of bytes
will be written at the same time. The internal programming
cycle is the same regardless of the number of bytes accessed.