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參數(shù)資料
| 型號(hào)： | WED2ZL361MSJ42BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 MULTI DEVICE SRAM MODULE, 4.2 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 0K |
| 代理商： | WED2ZL361MSJ42BC |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2ZL361MSJ
White Electronic Designs
1M x 36 Synchronous Pipeline Burst NBL SRAM
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
Address Bus
(SA0 – SA19)
DQa, DQb
DQPa, DQPb
DQc, DQd
DQPc, DQPd
DQa – DQd
DQPa – DQPd
1M x 18
CLK
CKE
ADV
LBO
CS1
CS2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CE1
CE2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
OE
WE
ZZ
BWd
BWa
BWc
BWb
1
2
3456
7
A
VDDQ
SA
VDDQ
B
NC
CE2
SA
ADV
SA
CE2
NC
C
NC
SA
VDD
SA
NC
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
E
DQc
VSS
CE1
VSS
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
DQc
BWc
SA
BWb
DQb
H
DQc
VSS
WE
VSS
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
VSS
CLK
VSS
DQa
L
DQd
BWd
NC
BWa
DQa
M
VDDQ
DQd
VSS
CKE
VSS
DQa
VDDQ
N
DQd
VSS
SA1
VSS
DQa
P
DQd
DQPd
VSS
SA0
VSS
DQPa
DQa
R
NC
SA
LBO
VDD
NC
SA
NC
T
NC
SA
ZZ
U
VDDQ
NC
VDDQ
FEATURES
n Fast clock speed: 250, 225, 200, 166, 150, 133MHz
n Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns
n Fast OE access times: 2.6, 2.8, 3.0, 3.5ns, 3.8ns, 4.2ns
n Separate +2.5V ± 5% power supplies for core, I/O
(VDD, VDDQ)
n Snooze Mode for reduced-standby power
n Individual Byte Write control
n Clock-controlled and registered addresses, data I/Os
and control signals
n Burst control (interleaved or linear burst)
n Packaging:
119-bump BGA package
JEDEC Pin Configuration
n Low capacitive bus loading
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed,
low-power CMOS designs that are fabricated using an
advanced CMOS process. WEDC’s 36Mb SyncBurst SRAMs
integrate two 1M x 18 SRAMs into a single BGA package
to provide 1M x 36 configuration. All synchronous inputs
pass through registers controlled by a positive-edge-
triggered single-clock input (CLK). The NBL or No Bus
Latency Memory utilizes all the bandwidth in any combi-
nation of operating cycles. Address, data inputs, and all
control signals except output enable and linear burst
order are synchronized to input clock. Burst order con-
trol must be tied “High or Low.” Asynchronous inputs
include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of
the clock input. This feature eliminates complex off-chip
write pulse generation and provides increased timing
flexibility for incoming signals.
NOTE: NBL (No Bus Latency) is equivalent to ZBT.
October 2002 Rev. 1
ECO # 15465
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED2ZL361MSJ-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NBL SSRAM MCP |
| WED2ZL361MV | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM |
| WED2ZL361MV35BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM |
| WED2ZL361MV35BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM |
| WED2ZL361MV38BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM |
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