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參數(shù)資料
| 型號(hào)： | WED3DG6432V7D1SGI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, ZMA144 |
| 封裝： | ROHS COMPLIANT, SODIMM-144 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 245K |
| 代理商： | WED3DG6432V7D1SGI |
WED3DG6432V-D1
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
January 2006
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY
Notes
1.
All voltages referenced to VSS.
2.
This parameter is sampled. VCC, VCCQ = +3.3V; f = 1 MHz; TA =
25C; pin under test based at 1.4V.
3.
ICC is dependent on output loading and cycle rates. Specied
values are obtained with minimum cycle time and the outputs
open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specications are used only to indicate cycle time at
which proper operation over the full temperature range is ensured
(Commercial temperature: 0C ≤ TA ≤ +70C and Industrial
Temperature: -40C ≤ TA ≤ +85C).
6.
An initial pause of 100μs is required after powerup, followed by
two AUTO REFRESH commands, up, followed by two AUTO
REFRESH commands,VCC and VCCQ must be powered up
simultaneously. VSS and VSSQ must be at the same potential.) The
two AUTO REFRESH command wake-ups should be repeated any
time the tREF refresh requirement is exceeded.
7.
AC characteristics assume tT = 1ns.
8.
In addition to meeting the transition rate specication, the clock
and CKE must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
9.
Outputs measured at 1.5V with equivalent load:
10.
t
HZ denes the time at which the output achieves the open circuit
condition; it is not a reference to VOH or VOL. The last valid data
element will meet tOH before going High-Z.
11.
AC timing and ICC test have VIL = 0V and VIH = 3V, with timing
referenced to 1.5V crossover point. If the input transition time
is longer than 1ns, then the timing is referenced at VIL(MAX) and
VIH(MIN) and no longer at the 1.5V crossover point.
12.
Other input signals are allowed to transition no more than once
every two clocks and are otherwise at valid VIH or VIL levels.
13.
ICC specications are tested after the device is properly initialized.
14.
Timing actually specied by tCKS; clock(s) specied as a reference
only at minimum cycle rate.
15.
Timing actually specied by tWR and tRP' clock(s) specied as a
reference only at minimum cycle rate.
16.
Timing actually specied by tWR.
17.
Required clocks are specied by JEDEC functionality and are not
dependent on any timing parameter.
18.
The ICC current will increase or decrease proportionally according
to the amount of frequency alteration for the test condition.
19.
Address transitions average one transition every two clocks.
20.
CLK must be toggled a minimum of two times during this period.
21.
Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 75.
22.
VIH overshoot: VIH(MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and
the pulse width cannot be greater than one third of the cycle rate.
VIL undershoot: VIL(MIN) = -2V for a pulse width ≤ 3ns.
23.
The clock frequency must remain constant (stable clock is defined
as a signal cycling within timing constraints specified for the clock
pin) during constraints specified for the clock pin) during in tWR,
and PRECHARGE commands). CKE may be used to reduce the
data rate.
24.
Auto precharge mode only. The precharge timing budget (tRP)
begins 7ns for 75; 7.5ns for 7 and 7ns for 10 after the first clock
delay, after the last WRITE is executed. May not exceed limit set
for precharge mode.
25.
Set for precharge mode.
26.
JEDEC and PC100 specify three clocks.
27.
tAC for 7/75 at CL = 3 with no load is 4.6ns and is guaranteed by
design.
28.
Parameter guaranteed by design.
29.
For 75, CL = 2 and tCK = 7.5ns; for 7, CL = 3 and tCK 7.5ns; for
10, CL= 2 and tCK = 10ns.
30.
CKE is HIGH during refresh command period tRFC(MIN) else CKE is
LOW. The ICC6 limit is actually a nominal value and does not result
in a fail value.
31.
Refer to component data sheet for timing waveforms.
32.
The value of tRAS used in 75 speed grade module SPDs is
calculated from tRC - tRP = 45ns.
33.
Leakage number reflects the worst case leakage possible through
the module pin, not what each memory device contributes.
Q
50pF
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| WED3DG6432V-D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB- 32Mx64 SDRAM UNBUFFERED |
| WED3DG6432V-D2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM Modules - 168 Pin DIMM. Unbuffered |
| WED3DG6433V-D1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM Modules - 144 Pin SO-DIMM. Unbuffered |
| WED3DG6433V-D2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM Modules - 168 Pin DIMM. Unbuffered |
| WED3DG6434V-D1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM Modules - 144 Pin SO-DIMM. Unbuffered |
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