參數(shù)資料
型號(hào)： WED9LAPC2C16P8BC
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： DRAM
英文描述： 4M X 32 SYNCHRONOUS DRAM, PBGA153
封裝： 14 X 22 MM, BGA-153
文件頁(yè)數(shù)： 20/21頁(yè)
文件大?。?/td> 693K
代理商： WED9LAPC2C16P8BC
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2B16P8BC
November 2001
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
SDRAM CURRENT STATE TRUTH TABLE (continued)
Current State
Command
Action
Notes
BRAS or
PRAS
BCAS or
PCAS
BWE or
PWE
BADDR12,
BADDR13
or PBS
BADDR or
PADDR
Description
Refreshing
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
Row Address
Bank Activate
ILLEGAL
H
L
BA
Column
Write
ILLEGAL
H
L
H
BA
Column
Read
ILLEGAL
H
L
X
Burst Termination
No Operation; Idle after tRC
H
X
No Operation
No Operation; Idle after tRC
Mode Register
Accessing
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
Row Address
Bank Activate
ILLEGAL
H
L
BA
Column
Write
ILLEGAL
H
L
H
BA
Column
Read
ILLEGAL
H
L
X
Burst Termination
ILLEGAL
H
X
No Operation
No Operation; Idle after two clock cycles
Notes:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if VCBS selects this bank then the action is illegal. If VCBS selects the bank not being referenced by the Current State
then the action may be legal depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satised.
4. The VCRAS# to VCCAS# Delay (tRCD) must occur before the command is given.
5. Address VCADDR9/AP is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank-to-bank delay time (tRRD) is not
satised.
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參數(shù)描述
WED9LAPC2C16P8BI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 32 SDRAM / 2M x 8 SDRAM
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