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參數(shù)資料
| 型號(hào)： | WED9LC6416V1510BI |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA153 |
| 封裝： | MO-163, BGA-153 |
| 文件頁(yè)數(shù)： | 24/27頁(yè) |
| 文件大?。?/td> | 370K |
| 代理商： | WED9LC6416V1510BI |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED9LC6416V
January 2001
Operation
Address Used
SSCE
SSADS
SSWE
SSOE
DQ
Deselected Cycle, Power Down
None
H
L
X
High-Z
WRITE Cycle, Begin Burst
External
L
X
D
READ Cycle, Begin Burst
External
L
H
L
Q
READ Cycle, Begin Burst
External
L
H
High-Z
READ Cycle, Suspend Burst
Current
X
H
L
Q
READ Cycle, Suspend Burst
Current
X
H
High-Z
READ Cycle, Suspend Burst
Current
H
L
Q
READ Cycle, Suspend Burst
Current
H
High-Z
WRITE Cycle, Suspend Burst
Current
X
H
L
X
D
WRITE Cycle, Suspend Burst
Current
H
L
X
D
NOTE:
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH
though out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
SSRAM OPERATION TRUTH TABLE
SSRAM PARTIAL TRUTH TABLE
Function
SSWE
BWE0
BWE1 BWE2
BWE3
READ
H
X
WRITE one Byte (DQ0-7)
L
H
WRITE all Bytes
L
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| WED9LC6416V1512BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1512BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1610BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1610BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1612BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
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