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參數資料
| 型號： | WEDPN16M72VR-125BC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, 5.8 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數： | 1/13頁 |
| 文件大?。?/td> | 161K |
| 代理商： | WEDPN16M72VR-125BC |
WEDPN16M72VR-XBX
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
1
November 2003 Rev. 4
The 128MByte (1Gb) SDRAM is a high-speed CMOS, dynamic
random-access, memory using 5 chips containing 268,435,456
bits. Each chip is internally configured as a quad-bank DRAM
with a synchronous interface. Each of the chip’s 67,108,864-
bit banks is organized as 8,192 rows by 512 columns by 16
bits. The MCP also incorporates two 16-bit universal bus
drivers for input control signals and addresses.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-12 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst
terminate option. An AUTO PRECHARGE function may be
enabled to provide a self-timed row precharge that is initiated
at the end of the burst sequence.
The 1Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compat-
ible with the 2
n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed,
random-access operation.
The 1Gb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along
with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, includ-
ing the ability to synchronously burst data at a high data rate
with automatic column-address generation, the ability to
interleave between internal banks in order to hide precharge
time and the capability to randomly change column ad-
dresses on each clock cycle during a burst access.
16MX72 REGISTERED SYNCHRONOUS DRAM
! Registered for enhanced performance of bus speeds
66, 100, 125, 133**MHz
! Package:
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
! Single 3.3V ±0.3V power supply
! Fully Synchronous; all signals registered on positive
edge of system clock cycle
! Internal pipelined operation; column address can be
changed every clock cycle
! Internal banks for hiding row access/precharge
! Programmable Burst length 1,2,4,8 or full page
! 8,192 refresh cycles
! Commercial, Industrial and Military Temperature Ranges
! Organized as 16M x 64
! Weight: WEDPN16M64VR-XBX - 2.5 grams typical
FEATURES
BENEFITS
! 47% SPACE SAVINGS
! Reduced part count
! Reduced I/O count
40% I/O Reduction
! Reduced trace lengths for lower parasitic capacitance
! Glueless connection to memory controller/PCI bridge
! Suitable for hi-reliability applications
! Laminate interposer for optimum TCE match
! Upgradeable to 32M x 72 density (contact factory for
information)
* This product is subject to change without notice.
* * Available at commercial and industrial temperatures only.
GENERAL DESCRIPTION
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相關代理商/技術參數 |
參數描述 |
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| WEDPN16M72VR-133B2C | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16MX72 REGISTERED SYNCHRONOUS DRAM |
| WEDPN16M72VR-133B2I | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16MX72 REGISTERED SYNCHRONOUS DRAM |
| WEDPN16M72VR-133B2M | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16MX72 REGISTERED SYNCHRONOUS DRAM |
| WEDPN16M72VR-66BC | 制造商:Microsemi Corporation 功能描述:16M X 72 SDRAM MODULE W/REGISTERED BUFFERS, 3.3V, 66 MHZ, 21 - Bulk |
| WEDPN16M72VR-66BI | 制造商:Microsemi Corporation 功能描述:16M X 72 SDRAM MODULE W/REGISTERED BUFFERS, 3.3V, 66 MHZ, 21 - Bulk |
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