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參數(shù)資料
| 型號： | WEDPN16M72VR-125BM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, 5.8 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 161K |
| 代理商： | WEDPN16M72VR-125BM |
WEDPN16M72VR-XBX
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
6
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
piece of output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge
n, and the
latency is
m clocks, the data will be available by clock edge
n+m. The I/Os will start driving as a result of the clock edge
one cycle earlier (
n + m - 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n
+ m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a READ command is
registered at T0 and the latency is programmed to two clocks,
the I/Os will start driving after T1 and the data will be valid by
T2. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
The normal operating mode is selected by setting M7and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because
unknown operation or incompatibility with future versions
may result.
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
The Truth Table provides a quick reference of available com-
mands. This is followed by a written description of each
command. Three additional Truth Tables appear following the
Operation section; these tables provide current state/next
state information.
FIG. 4 CAS LATENCY
CAS LATENCY
OPERATING MODE
WRITE BURST MODE
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHZ)
CAS
SPEED
LATENCY = 2
LATENCY = 3
-66
≤ 50
≤ 66
-100
≤ 66
≤ 100
-125
≤ 100
≤ 125
-133
≤ 100
≤ 133
COMMANDS
CLK
Command
I/O
CLK
Command
I/O
T0
T1
T2
T3
T0
T1
T2
T3
T4
READ
NOP
CAS Latency = 2
DOUT
tLZ
tOH
tAC
READ
NOP
DOUT
tLZ
tOH
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
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