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| 型號(hào)： | WEDPN4M64V-125BM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 4M X 64 SYNCHRONOUS DRAM, 6 ns, PBGA219 |
| 封裝： | 21 X 21 MM, PLASTIC, BGA-219 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大小： | 385K |
| 代理商： | WEDPN4M64V-125BM |
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIGURE 3 – CAS LATENCY
CK
I/O
T2
T1
T3
T0
COMMAND
NOP
READ
NOP
CK
I/O
T2
T1
T3
T0
CAS Latency = 2
LZ
DOUT
tOH
COMMAND
NOP
READ
tAC
NOP
t
CAS Latency = 3
tAC
T4
DON’T CARE
UNDEFINED
LZ
DOUT
tOH
t
OPERATING MODE
The normal operating mode is selected by setting M7and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
TABLE 2 – CAS LATENCY
SPEED
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS LATENCY = 2
CAS LATENCY = 3
-100
≤ 75
≤ 100
-125
≤ 100
≤ 125
-133
≤ 100
≤ 133
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
rst piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n+m. The I/Os will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency is
programmed to two clocks, the I/Os will start driving after
T1 and the data will be valid by T2. Table 2 below indicates
the operating frequencies at which each CAS latency setting
can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| WEDPN4M64V-133BC | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:4Mx64 Synchronous DRAM |
| WEDPN4M64V-133BI | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:4Mx64 Synchronous DRAM |
| WEDPN4M64V-133BM | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:4Mx64 Synchronous DRAM |
| WEDPN4M64V-XBX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SDRAM MCP |
| WEDPN4M72LV-100B2I | 制造商:Microsemi Corporation 功能描述:UCKT,SDRAM 4MX72,219BGA,4M72V - Bulk 制造商:White Electronic Designs 功能描述: |
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