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參數(shù)資料
| 型號： | WEDPZ512K72S-XBX |
| 英文描述： | NBL SSRAM MCP |
| 中文描述： | NBL的的SSRAM MCP的 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 227K |
| 代理商： | WEDPZ512K72S-XBX |
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPZ512K 72S-X BX
150
MHz
(Max) (Max) (Max)
700
650
133
MHz
100
MHz
Description
Symbol Conditions
Units Notes
Power Supply
Current: Operating
Power Supply
Current: Standby
I
DD
Device Selected; All Inputs
≤
V
IL
or
≥
V
IH
; Cycle
Time
≥
T
CYC
MIN; V
DD
= MAX; Output Open
Device Deselected; V
DD
= MAX; All Inputs
≤
V
IL or
≥
V
IH
All Inputs Static; CLK Frequency = MAX
Output Open, ZZ
≥
V
DD -
0.2V
Device Deselected; V
DD
= MAX; All Inputs
≤
V
SS
+ 0.2 or V
DD
- 0.2; f = max ; ZZ
≤
V
IL
600
mA
1
I
SB2
120
120
120
mA
Clock Running
Standby Current
I
SB
180
180
160
mA
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
V
IN
Voltage or any other pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature (BGA)
-0.3V to + 3.6V
-0.3V to + 3.6V
-55°C to + 150°C
E
LECTRICAL
C
HARACTERISTICS
(-55°C - TA - +125°C)
*Stress greater than those listed under “Absolute Maximum Ratings: may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating condtions for extended periods may affect reliability.
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
I/O Power Suply
NOTES:
1. All voltages referenced to V
SS
(GND)
2. ZZ pin has an internal pull-up, and input leakage = ± 20 μA.
Symbol
V
IH
V
IL
I
IL
I
LO
V
OH
V
OL
V
DD
V
DDQ
Conditions
Min
1.7
-0.3
-4
-2
2.0
---
2.375
2.375
Max
Units
V
V
μA
μA
V
V
V
V
Notes
1
1
2
V
DD
+ 0.3
0.7
+4
+2
---
0.4
2.625
2.625
V
DD =
M
ax,
0V - V
IN
- V
DD
Output(s) Disabled, V
OUT
= V
SS
to V
DDQ
I
OH
= -1.0mA
I
OL
= 1.0mA
1
1
1
1
DC C
HARACTERISTICS
(-55°C - TA - + 125°C)
BGA C
APACITANCE
(T
A
= + 25°C, f = 1MH
Z
)
NOTES: 1. Ths parameteris not tested but guaranteed by design.
Description
Control Input Capacitance (LBO, zz)
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
Symbol Max Units Notes
C
IC
16
C
I
8
C
O
10
C
A
16
C
CK
6
pF
pF
pF
pF
pF
1
1
1
1
1
NOTES: 1. I
DD
is specified with no output current and increases with fastercycle times.
I
DD
increases with fastercycle times and greateroutput loading.
T
HERMAL
R
ESISTANCE
Parameter
Thermal Resistance: Die Junction to Ambient
Thermal Resistance: Die Junction to Ball
Thermal Resistance: Die Junction to Case
Symbol Max
θ
JA
θ
JB
θ
JC
Unit
28.7 °C/W
16.0 °C/W
7.1
°C/W
Note: Refer to Application Note “PBGA Thermal Resistance Corrleation”
for further information regarding WEDC’s thermal modeling.
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