參數(shù)資料
型號(hào)： WF128K16
英文描述： 5V 128Kx16 Flash Module(5V 128Kx16閃速存儲(chǔ)器模塊)
中文描述： 5V的128Kx16閃存模塊（5V的128Kx16閃速存儲(chǔ)器模塊）
文件頁(yè)數(shù)： 1/11頁(yè)
文件大小： 186K
代理商： WF128K16
White Microelectronics Phoenix, AZ (602) 437-1520
7
F
1
WF128K16, WF256K16-XCX5
FEATURES
I
Access Times of 50, 60, 70, 90, 120 and 150ns
I
40 pin Ceramic DIP (Package 303)
I
Organized as 128Kx16 and 256Kx16
I
Sector Architecture
8 equal size sectors of 16KBytes each per chip
Any combination of sectors can be concurrently erased.
Also supports full chip erase
I
100,000 Erase/Program Cycles Minimum (0
°
C to 70
°
C)
I
Data Retention, 10 Years at 125
°
C
I
Commercial, Industrial and Military Temperature Ranges
5V FLASH MODULE
PRELIMINARY *
I
5 Volt Programming; 5V
±
10% Supply
I
Low Power CMOS
I
Embedded Erase and Program Algorithms
I
TTL Compatible Inputs and CMOS Outputs
I
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
I
Page Program Operation and Internal Program Control Time
*
This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note: Programming information available upon request.
FIG. 1
PIN CONFIGURATION AND BLOCK DIAGRAM
TOP VIEW
A
0
-
16
I/O
0-15
CS
1
-
2
OE
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
PIN DESCRIPTION
128K x 8
128K x 8
A
0-16
OE
WE
CS
1
CS
2
128K x 8
128K x 8
I/O
8-15
I/O
0-7
(1)
(1)
NOTE:
1. CS
1
and CS
2
are used to select the lower and upper 128Kx16 of the
device. CS
1
and CS
2
must not be enabled at the same time.
BLOCK DIAGRAM
FOR WF256K16-XCX5
BLOCK DIAGRAM
FOR WF128K16-XCX5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CS2*/NC
CS1
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE
V
CC
WE
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
128K x 8
A
0-16
OE
WE
CS
1
128K x 8
I/O
8-15
I/O
0-7
*
CS
2
for 256Kx16 and NC for 128Kx16
October 1998
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