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參數(shù)資料
| 型號： | WM2629 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Octal 8-bit, Serial Input, Voltage Output DAC with Power Down |
| 中文描述： | 八進制8位，串行輸入，電壓與掉電輸出DAC |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 119K |
| 代理商： | WM2629 |
Production Data
WM2629
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
5
Test Characteristics
:
Over recommended operating conditions (unless noted otherwise).
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High level input current
I
IH
Input voltage = DVDD
1
μ
A
Low level input current
I
IL
Input voltage = 0V
-1
μ
A
Input capacitance
C
I
8
pF
Digital Output
High level digital output voltage
V
OH
Load = 10k
2.6
V
Low level digital output voltage
V
OL
Load = 10k
0.4
V
Output voltage rise time
Load = 10k
, 20pF, includes
propagation delay
7
20
ns
Notes
:
1.
Integral non-linearity (INL)
is the maximum deviation of the output from the line between zero and full scale excluding
the effects of zero code and full scale errors).
2.
Differential non-linearity (DNL)
is the difference between the measured and ideal 1LSB amplitude change
of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same
direction (or remains constant) as a change in digital input code.
3.
Zero code error
is the voltage output when the DAC input code is zero.
4.
Gain error
is the deviation from the ideal full-scale output excluding the effects of zero code error.
5.
Power supply rejection ratio
is measured by varying AVDD from 4.5V to 5.5V and measuring the
proportion of this signal imposed on the zero code error and the gain error.
6.
Zero code error
and
Gain error
temperature coefficients are normalised to full-scale voltage.
7.
Output load regulation
is the difference between the output voltage at full scale with a 10k
load and 2k
load. It is expressed as a percentage of the full scale output voltage with a 10k
load.
8.
I
DD
is measured while continuously writing code 128 to the DAC. For V
IH
< DVDD - 0.7V and V
IL
> 0.7V
supply current will increase.
9.
Slew rate results
are for the lower value of the rising and falling edge slew rates.
10.
Settling time
is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested.
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