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參數(shù)資料
| 型號： | WM2633CDT |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Byte-wide Parallel Input, 12-bit Voltage Output DAC with Internal Reference |
| 中文描述： | 字節(jié)寬并行輸入，12位電壓輸出DAC，帶有內(nèi)部參考 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 389K |
| 代理商： | WM2633CDT |
Production Data
WM2633
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 1999
9
PARALLEL INTERFACE
The device latches data on the positive edge of NWE. It must be enabled with NCS low. Whether the
data is written to one of the DAC holding latches (MSW, LSW) or the control register, depends on the
address bits A1 and A0. NLDAC low updates the DAC with the value in the holding latch. NLDAC is
an asynchronous input and can be held low, if a synchronous update is not necessary. Alternatively,
the RLDAC bit of the control register can be used to synchonously update the DAC latch via software
control.
D[0-7]
A[0-1]
NCS
NWE
NLDAC
X
MSW
LSW
X
X
1
0
X
X
Figure 7 Example of a Complete Write Cycle Using NLDAC to Update the DAC
D[0-7]
A[0-1]
NCS
NWE
NLDAC
X
MSW
LSW
X
0
1
X
Control
X
X
X
3
X
X
Figure 8 Example of a Complete Write Cycle Using the Control Word to Update the DAC
. If NLDAC is held high as
shown above, the DAC latch is normally closed, but can be made transparent by setting the RLDAC control register bit
high. The procedure shown assumes that the RLDAC bit is low at the start and is written high on the final write.
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| WM2637 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:Dual 10-Bit Serial Input Voltage Output DAC with Internal Reference |
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