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參數(shù)資料
| 型號： | WM8181 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 12-bit 2MSPS Serial Output CIS/CCD Digitiser |
| 中文描述： | 12位2MSPS串行輸出獨聯(lián)體/防治荒漠化公約數(shù)字化儀 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 150K |
| 代理商： | WM8181 |
WM8181
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 January 2000
2
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
XWM8181CDW
0 to 70
o
C
16-pin SOIC wide
body
DVDD
AGND2
2
15
AVDD
AGND1
1
16
DOUT
VREFIN
3
14
MCLK
VINP
4
13
VSMP
VINM
5
12
CLAMP
VRB
6
11
DGND
VRT
7
10
9
8
NC
NC
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
AGND1
Ground
General analogue ground (0V).
2
AGND2
Ground
Reference analogue ground (0V).
3
VREFIN
Analogue input
Allows external control of the ADC references.
4
VINP
Analogue input
Positive video input
5
VINM
Analogue input
Negative video input
Usually one of VINP or VINM will be an externally
applied d.c. bias, the other will be a signal voltage.
6
VRB
Analogue output
Lower reference voltage. This pin must be connected to AGND and VRT via
decoupling capacitors. See Recommended External Components section for details.
Upper reference voltage. This pin must be connected to AGND and VRB via
decoupling capacitors. See Recommended External Components section for details.
No internal connection
7
VRT
Analogue output
8
NC
9
NC
No internal connection
10
DGND
Ground
Digital ground (0V).
11
CLAMP
Digital input
Connects VINP and VINM together, active high.
12
VSMP
Digital input
Video sample synchronisation pulse, at input pixel rate. Sampled on rising edge of
MCLK. See Operational Timing Diagrams for details.
Master clock. This clock can be applied at either 12 or 16 times the input pixel rate.
13
MCLK
Digital input
14
DOUT
Digital output
ADC serial data output, changes on falling edge of MCLK.
15
DVDD
Supply
Digital supply (3.3V, 5V).
16
AVDD
Supply
Analogue supply (3.3V, 5V).
POSSIBLE POWER SUPPLY COMBINATIONS
COMBINATION
1
2
3
AVDD (VOLTS)
5
3.3
5
DVDD (VOLTS)
5
3.3
3.3
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