參數(shù)資料
型號: WM8190
廠商: Wolfson Microelectronics
英文描述: TVS UNIDIRECT 6V 400W SMA
中文描述: (8 6)位輸出14位獨聯(lián)體/防治荒漠化公約AFE的/數(shù)字轉換器
文件頁數(shù): 2/25頁
文件大?。?/td> 438K
代理商: WM8190
WM8190
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 August 1999
2
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
XWM8190CDW/V
0 to 70
o
C
28-pin SOIC
SEN
OP[1]
OP[0]
SCK
SDI
DVDD2
OP[7]/SDO
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
GINP
AGND1
VRB
VRT
VRX
VRLC/VBIAS
BINP
AVDD
DGND
AGND2
DVDD1
OEB
VSMP
RLC/ACYC
MCLK
RINP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN DESCRIPTION
PIN
1
2
3
NAME
RINP
AGND2
DVDD1
TYPE
DESCRIPTION
Red channel input video.
Analogue ground (0V).
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
Output Hi-Z control, all digital outputs disabled when OEB = 1.
Video sample synchronisation pulse.
RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if
used on every pixel. ACYC autocycles between R, G, B inputs.
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
Digital ground (0V).
Enables the serial interface when high.
Digital supply (5V/3.3V), all digital I/O pins.
Serial data input.
Serial clock.
Analogue input
Supply
Supply
4
5
6
OEB
VSMP
RLC/ACYC
Digital input
Digital input
Digital input
7
MCLK
Digital input
8
9
10
11
12
DGND
SEN
DVDD2
SDI
SCK
Supply
Digital input
Supply
Digital input
Digital input
Digital multiplexed output data bus.
ADC output data (d13:d0) and error flags (F) are available in three multiplexed
formats as shown, under the control of register bit MUXOP[1:0].
See ‘Output Formats’ description in Device Description section for further details.
8+6-bit
7+7-bit
4+4+4+2-bit
B
A
d6
d7
d8
d9
d10
d11
d12
d13
Alternatively, pin OP[7]/SDO may be used to output register read-back data when
OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device
Description section for further details.
B
F
F
d0
d1
d2
d3
d4
d5
A
F
d7
d8
d9
d10
d11
d12
d13
B
F
d0
d1
d2
d3
d4
d5
d6
A
C
D
13
14
15
16
17
18
19
20
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
d10
d11
d12
d13
d6
d7
d8
d9
d2
d3
d4
d5
F
F
d0
d1
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