參數(shù)資料
型號: WM8192
廠商: Wolfson Microelectronics
英文描述: TVS UNIDIRECT 400W 6.5V SMA
中文描述: (8)位輸出16位獨聯(lián)體/防治荒漠化公約AFE的/數(shù)字轉(zhuǎn)換器
文件頁數(shù): 22/24頁
文件大小: 619K
代理商: WM8192
WM8192
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WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 June 2000
22
REGISTER
BIT
NO
0
BIT
NAME(S)
VSMPDET
DEFAULT
DESCRIPTION
0
0 = Normal operation, signal on VSMP input pin is applied directly to
Timing Control block.
1 = Programmable VSMP detect circuit is enabled. An internal
synchronisation pulse is generated from signal applied to VSMP input pin
and is applied to Timing Control block.
When VSMPDET = 0 these bits have no effect.
When VSMPDET = 1 these bits set a programmable delay from the
detected edge of the signal applied to the VSMP pin. The internally
generated pulse is delayed by VDEL MCLK periods from the detected
edge.
See Figure 13, Internal VSMP Pulses Generated for details.
When VSMPDET = 0 this bit has no effect.
When VSMPDET = 1 this bit controls whether positive or negative edges
are detected:
0 = Negative edge on VSMP pin is detected and used to generate internal
timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate internal
timing pulse.
See Figure 13 for further details.
Selective power disable register - activated when SELPD = 1.
Each bit disables respective cell when 1, enabled when 0.
SELDIS[0] = Red CDS, PGA
SELDIS[1] = Green CDS, PGA
SELDIS[2] = Blue CDS, PGA
SELDIS[3] = ADC
Red channel offset DAC value.
3:1
VDEL[2:0]
000
Setup
Register 5
4
POSNNEG
0
Setup
Register 6
3:0
SELDIS[3:0]
0000
Offset DAC
(Red)
7:0
DAC[7:0]
0
Offset DAC
(Green)
Offset DAC
(Blue)
Offset DAC
(RGB)
PGA gain
(Red)
7:0
DAC[7:0]
0
Red channel offset DAC value
7:0
DAC[7:0]
0
Red channel offset DAC value
7:0
DAC[7:0]
0
A write to this register location causes the red, green and blue offset DAC
registers to be overwritten by the new value
7:0
PGA[7:0]
0
Determines the gain of the red channel PGA according to the equation:
Red channel PGA gain = 208/(283-PGA[7:0])
Determines the gain of the green channel PGA according to the equation:
Green channel PGA gain = 208/(283-PGA[7:0])
Determines the gain of the blue channel PGA according to the equation:
Blue channel PGA gain = 208/(283-PGA[7:0])
A write to this register location causes the red, green and blue PGA gain
registers to be overwritten by the new value
PGA gain
(Green)
7:0
PGA[7:0]
0
PGA gain
(Blue)
7:0
PGA[7:0]
0
PGA gain
(RGB)
7:0
PGA[7:0]
0
Table 6 Register Control Bits
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