參數(shù)資料
型號: WMS128K8L-120FEMA
元件分類: SRAM
英文描述: 128K X 8 STANDARD SRAM, 120 ns, CDFP32
封裝: CERAMIC, FP-32
文件頁數(shù): 3/8頁
文件大?。?/td> 101K
代理商: WMS128K8L-120FEMA
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
3
WMS128K8-XXX
Parameter
Symbol
-70
-85
-100
-120
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
70
85
100
120
ns
Address Access Time
tAA
70
85
100
120
ns
Output Hold from Address Change
tOH
33
3
ns
Chip Select Access Time
tACS
70
85
100
120
ns
Output Enable to Output Valid
tOE
35
45
50
60
ns
Chip Select to Output in Low Z
tCLZ1
55
5
ns
Output Enable to Output in Low Z
tOLZ1
55
5
ns
Chip Disable to Output in High Z
tCHZ1
25
35
ns
Output Disable to Output in High Z
tOHZ1
25
35
ns
1. This parameter is guaranteed by design but not tested.
I
Current Source
D.U.T.
C
= 50 pf
eff
I
OL
V
1.5V
(Bipolar Supply)
Z
Current Source
OH
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
AC CHARACTERISTICS
(VCC = 5.0V, TA = -55
°C To +125°C)
AC CHARACTERISTICS
(VCC = 5.0V, TA = -55
°C To +125°C)
Parameter
Symbol
-70
-85
-100
-120
Units
Write Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
70
85
100
120
ns
Chip Select to End of Write
tCW
60
75
80
100
ns
Address Valid to End of Write
tAW
60
75
80
100
ns
Data Valid to End of Write
tDW
30
35
40
50
ns
Write Pulse Width
tWP
50
55
70
80
ns
Address Setup Time
tAS
0
000
ns
Address Hold Time
tAH
5
555
ns
Output Active from End of Write
tOW1
5
555
ns
Write Enable to Output in High Z
tWHZ1
25
30
35
ns
Data Hold Time
tDH
0
000
ns
1. This parameter is guaranteed by design but not tested.
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