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參數(shù)資料
| 型號： | WMS128K8L55DRM |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 55 ns, CDSO32 |
| 封裝： | CERAMIC, SOJ-32 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 133K |
| 代理商： | WMS128K8L55DRM |
3
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
WMS128K8-XXX
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
I
Current Source
D.U.T.
C
= 50 pf
eff
I
OL
V
≈ 1.5V
(Bipolar Supply)
Z
Current Source
OH
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Parameter
Symbol
-15
-17
-20
-25
-35
-45
-55
Units
Read Cycle
Min
Max
Min
Max Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
15
17
20
25
35
45
55
ns
Address Access Time
tAA
15
17
20
25
35
45
55
ns
Output Hold from Address Change
tOH
0
000
00
ns
Chip Select Access Time
tACS
15
17
20
25
35
45
55
ns
Output Enable to Output Valid
tOE
10
12
15
20
25
30
ns
Chip Select to Output in Low Z
tCLZ1
3
333
33
ns
Output Enable to Output in Low Z
tOLZ1
0
000
00
ns
Chip Disable to Output in High Z
tCHZ1
10
12
20
ns
Output Disable to Output in High Z
tOHZ1
10
12
20
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-15
-17
-20
-25
-35
-45
-55
Units
Write Cycle
Min
Max
Min Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
15
17
20
25
35
45
55
ns
Chip Select to End of Write
tCW
14
15
20
25
30
45
ns
Address Valid to End of Write
tAW
14
15
20
25
30
45
ns
Data Valid to End of Write
tDW
10
12
15
20
25
ns
Write Pulse Width
tWP
14
15
20
25
30
45
ns
Address Setup Time
tAS
00
0
ns
Address Hold Time
tAH
00
0
ns
Output Active from End of Write
tOW1
33
4
ns
Write Enable to Output in High Z
tWHZ1
10
12
15
20
25
ns
Data Hold Time
tDH
00
0
ns
1. This parameter is guaranteed by design but not tested.
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| WMS128K8L17DJIA | 128K X 8 STANDARD SRAM, 17 ns, CDSO36 |
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| WMS128K8L55CC | 128K X 8 STANDARD SRAM, 55 ns, CDIP32 |
| WMS128K8L55DJI | 128K X 8 STANDARD SRAM, 55 ns, CDSO36 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WMS128K8L-55DRM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|128KX8|CMOS|SOJ|32PIN|CERAMIC |
| WMS128K8L-55DRMA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| WMS128K8L-55DRME | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| WMS128K8L-55FC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|128KX8|CMOS|FP|36PIN|CERAMIC |
| WMS128K8L-55FCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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