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參數(shù)資料
| 型號： | WMS256K16-20DLMA |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 20 ns, CDSO44 |
| 封裝： | CERAMIC, SOJ-44 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 109K |
| 代理商： | WMS256K16-20DLMA |
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WMS256K16-XXX
I
Current Source
D.U.T.
C
= 50 pf
eff
I
OL
V
≈ 1.5V
(Bipolar Supply)
Z
Current Source
OH
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-17
-20
-25
-35
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
17
20
25
35
ns
Address Access Time
tAA
17
20
25
35
ns
Output Hold from Address Change
tOH
0
000
ns
Chip Select Access Time
tACS
17
20
25
35
ns
Output Enable to Output Valid
tOE
10
12
15
20
ns
Chip Select to Output in Low Z
tCLZ1
2
555
ns
Output Enable to Output in Low Z
tOLZ1
0
000
ns
Chip Disable to Output in High Z
tCHZ1
910
1215
ns
Output Disable to Output in High Z
tOHZ1
910
1215
ns
LB, UB Access Time
tBA
10
12
14
17
ns
LB, UB Enable to Low Z Output
tBLZ1
0
000
ns
LB, UB Disable to High Z Output
tBHZ1
910
1215
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-17
-20
-25
-35
Units
Write Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
17
20
25
35
ns
Chip Select to End of Write
tCW
14
17
20
25
ns
Address Valid to End of Write
tAW
14
17
20
25
ns
Data Valid to End of Write
tDW
10
12
15
20
ns
Write Pulse Width
tWP
14
17
20
25
ns
Address Setup Time
tAS
0000
ns
Address Hold Time
tAH
2222
ns
Output Active from End of Write
tOW1
0000
ns
Write Enable to Output in High Z
tWHZ1
91010
15
ns
Data Hold Time
tDH
0000
ns
LB, UB Valid to End of Write
tBW
14
17
20
25
ns
1. This parameter is guaranteed by design but not tested.
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| WMS256K16L-35DLI | 256K X 16 STANDARD SRAM, 35 ns, CDSO44 |
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| WMS256K16-35FLIA | 256K X 16 STANDARD SRAM, 35 ns, CDFP44 |
| WMS256K16-20FGC | 256K X 16 STANDARD SRAM, 20 ns, CDSO44 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WMS256K16-20FGC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256Kx16 MONOLITHIC SRAM, SMD 5962-96902 |
| WMS256K16-20FGCA | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256Kx16 MONOLITHIC SRAM, SMD 5962-96902 |
| WMS256K16-20FGI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256Kx16 MONOLITHIC SRAM, SMD 5962-96902 |
| WMS256K16-20FGIA | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256Kx16 MONOLITHIC SRAM, SMD 5962-96902 |
| WMS256K16-20FGM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256Kx16 MONOLITHIC SRAM, SMD 5962-96902 |
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