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參數(shù)資料
| 型號： | WMS512K8L-15DJCA |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 15 ns, CDSO36 |
| 封裝： | CERAMIC, SOJ-36 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 114K |
| 代理商： | WMS512K8L-15DJCA |
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WMS512K8-XXX
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-15
-17
-20
-25
-35
-45
-55
Units
Read Cycle
Min
Max
Min
Max
Min Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
15
17
20
25
35
45
55
ns
Address Access Time
tAA
15
17
20
25
35
45
55
ns
Output Hold from Address Change
tOH
0
000
0
ns
Chip Select Access Time
tACS
15
17
20
25
35
45
55
ns
Output Enable to Output Valid
tOE
8
9
10
12
25
ns
Chip Select to Output in Low Z
tCLZ1
2
244
4
ns
Output Enable to Output in Low Z
tOLZ1
0
000
0
ns
Chip Disable to Output in High Z
tCHZ1
8
9
10
12
15
20
ns
Output Disable to Output in High Z
tOHZ1
8
9
10
12
15
20
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-15
-17
-20
-25
-35
-45
-55
Units
Write Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
15
17
20
25
35
45
55
ns
Chip Select to End of Write
tCW
13
14
15
25
35
50
ns
Address Valid to End of Write
tAW
13
14
15
25
35
50
ns
Data Valid to End of Write
tDW
8
9
10
20
25
ns
Write Pulse Width
tWP
13
14
15
25
35
40
ns
Address Setup Time
tAS
2
222
ns
Address Hold Time
tAH
0
055
ns
Output Active from End of Write
tOW1
2
3
4
455
ns
Write Enable to Output in High Z
tWHZ1
89
9
10
15
20
25
ns
Data Hold Time
tDH
0
000
ns
1. This parameter is guaranteed by design but not tested.
I
Current Source
D.U.T.
C
= 50 pf
eff
I
OL
V
≈ 1.5V
(Bipolar Supply)
Z
Current Source
OH
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WMS512K8L-35DJMA | 512K X 8 STANDARD SRAM, 35 ns, CDSO36 |
| WMS512K8L-45DJM | 512K X 8 STANDARD SRAM, 45 ns, CDSO36 |
| WMS512K8-45CLI | 512K X 8 STANDARD SRAM, 45 ns, CQCC32 |
| WMS512K8L-55FEIA | 512K X 8 STANDARD SRAM, 55 ns, CDFP32 |
| WMS512K8-15FEC | 512K X 8 STANDARD SRAM, 15 ns, CDFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WMS512K8L-15DJI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kx8 MONOLITHIC SRAM |
| WMS512K8L-15DJIA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kx8 MONOLITHIC SRAM |
| WMS512K8L-15DJM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kx8 MONOLITHIC SRAM |
| WMS512K8L-15DJMA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kx8 MONOLITHIC SRAM |
| WMS512K8L-15DJQ | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx8 MONOLITHIC SRAM, SMD 5962-95613 |
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