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參數(shù)資料
| 型號： | WP2002A-Y-JCS |
| 廠商： | DB Lectro Inc. |
| 英文描述： | WP2002A-Y-JCS |
| 中文描述： | WP2002A - Y型參聯(lián)會 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 267K |
| 代理商： | WP2002A-Y-JCS |
第 8 頁，共 18 頁
9.Function Description
The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an
instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information
for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written
from the MPU.
The DR temporarily stores data to be written or read from DDRAM or
CGRAM.
When address information is written into the IR, then data is stored into the DR from
DDRAM or CGRAM.
By the register selector (RS) signal, these two registers can be selected.
RS
R/W
Operation
0
IR write as an internal operation (display clear, etc.)
0
1
Read busy flag (DB7) and address counter (DB0 to DB7)
1
0
Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM)
1
Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR)
Busy Flag (BF)
When the busy flag is 1, the controller LSI is in the internal operation mode, and the next
instruction will not be accepted.
When RS=0 and R/W=1, the busy flag is output to DB7.
The
next instruction must be written after ensuring that the busy flag is 0.
Address Counter (AC)
The address counter (AC) assigns addresses to both DDRAM and CGRAM
Display Data RAM (DDRAM)
This DDRAM is used to store the display data represented in 8-bit character codes.
Its extended
capacity is 80×8 bits or 80 characters.
Below figure is the relationships between DDRAM
addresses and positions on the liquid crystal display.
AC
(hexadecimal)
High bits
Low bits
AC6 AC5 AC4 AC3 AC2 AC1 AC0
1
0
1
0
Example: DDRAM addresses 4E
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