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參數(shù)資料
| 型號： | WSE128K16-42H1MA |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, CHIP66 |
| 封裝： | CERAMIC, HIP-66 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 299K |
| 代理商： | WSE128K16-42H1MA |
6
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
WSE128K16-XXX
EEPROM WRITE
A write cycle is initiated when OE is high and a low pulse is on
EWE or ECS with ECS or EWE low. The address is latched on the
falling edge of ECS or EWE whichever occurs last. The data is
latched by the rising edge of ECS or EWE, whichever occurs first.
A byte write operation will automatically continue to completion.
WRITE CYCLE TIMING
Figures 7 and 8 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the ECS
line low. Write enable consists of setting the EWE line low.
The write cycle begins when the last of either ECS or EWE goes
low.
The EWE line transition from high to low also initiates an
internal 150
sec delay timer to permit page mode operation.
Each subsequent EWE transition from high to low that occurs
before the completion of the 150
sec time out will restart the
timer from zero. The operation of the timer is the same as a
retriggerable one-shot.
EEPROM AC WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
Write Cycle Parameter
Symbol
Min
Max
Unit
Write Cycle Time, TYP = 6ms
tWC
10
ms
Address Set-up Time
tAS
0ns
Write Pulse Width (EWE or ECS)
tWP
150
ns
Chip Select Set-up Time
tCS
0ns
Address Hold Time
tAH
100
ns
Data Hold Time
tDH
10
ns
Chip Select Hold Time
tCSH
0ns
Data Set-up Time
tDS
100
ns
Output Enable Set-up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
Write Pulse Width High
tWPH
50
ns
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| WSE128K16-73G2TM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx16 SRAM/EEPROM MODULE |
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