參數(shù)資料
型號: WSF512K16X-39G2CA
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, CQMA68
封裝: 22 MM SQUARE, HERMETIC SEALED, CERAMIC, QFP-68
文件頁數(shù): 1/14頁
文件大?。?/td> 146K
代理商: WSF512K16X-39G2CA
11
MIXED
MODULES
1
White Microelectronics Phoenix, AZ (602) 437-1520
WSF512K16-XXX
512KX16 SRAM/FLASH MODULE, SMD 5962-96901
FEATURES
s Access Times of 35ns (SRAM) and 90ns (FLASH)
s Access Times of 70ns (SRAM) and 120ns (FLASH)
s Packaging
66-pin, PGA Type, 1.385 inch square HIP, Hermetic
Ceramic HIP (Package 402)
68-lead, Hermetic CQFP (G2), 22mm (0.880 inch) square
(Package 500).
Designed to fit JEDEC 68 lead 0.990” CQFJ footprint (Fig. 2)
s 512Kx16 SRAM
s 512Kx16 5V FLASH
s Organized as 512Kx16 of SRAM and 512Kx16 of Flash
Memory with separate Data Busses
s Both blocks of memory are User Configurable as 1Mx8
s Low Power CMOS
s Commercial, Industrial and Military Temperature Ranges
s TTL Compatible Inputs and Outputs
s Built-in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
s Weight - 13 grams typical
FIG. 1 PIN CONFIGURATION FOR WSF512K16-XH2X
FWE FCS
SWE SCS
512K x 8
SRAM
8
SD 0-7
1
512K x 8
SRAM
8
SD 8-15
2
512K x 8
FLASH
8
FD 0-7
1
512K x 8
FLASH
8
FD 8-15
2
A 0- 18
OE
SWE SCS
PIN DESCRIPTION
FD0-15
Flash Data Inputs/Outputs
SD0-15
SRAM Data Inputs/Outputs
A0-18
Address Inputs
SWE1-2
SRAM Write Enable
SCS1-2
SRAM Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
FWE1-2
Flash Write Enable
FCS1-2
Flash Chip Select
SD8
SD9
SD10
A13
A14
A15
A16
A18
SD0
SD1
SD2
SWE2
SCS2
GND
SD11
A10
A11
A12
VCC
SCS1
NC
SD3
SD15
SD14
SD13
SD12
OE
A17
SWE1
SD7
SD6
SD5
SD4
FD8
FD9
FD10
A6
A7
NC
A8
A9
FD0
FD1
FD2
VCC
FCS2
FWE2
FD11
A3
A4
A5
FWE1
FCS1
GND
FD3
FD15
FD14
FD13
FD12
A0
A1
A2
FD7
FD6
FD5
FD4
11
22
33
44
55
66
1
12
23
34
45
56
TOP VIEW
FLASH MEMORY FEATURES
s 10,000 Erase/Program Cycles
s Sector Architecture
8 equal size sectors of 64K bytes each
Any combination of sectors can be concurrently erased.
Also supports full chip erase
s 5 Volt Programming; 5V
± 10% Supply
s Embedded Erase and Program Algorithms
s Hardware and Software Write Protection
s Page Program Operation and Internal Program Control Time.
Note: Programming information available upon request.
November 1997
BLOCK DIAGRAM
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