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參數(shù)資料
| 型號(hào)： | WV3EG265M64EFSU262D4-S |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | SODIMM-200 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大小： | 148K |
| 代理商： | WV3EG265M64EFSU262D4-S |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs WV3EG265M64EFSU-D4
October 2005
Rev. 1
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°c
≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Symbol
Conditions
DDR333 @
CL = 2.5
DDR266 @
CL = 2
DDR266 @
CL = 2.5
Unit
Operating current
IDD0*
One device bank active; Active-Precharge; tRC = tRC(MIN);
tCK = tCK(MIN); DQ, DM and DQS inputs change once per clock
cycle; Address and control inputs change once every two
clock cycles
136012401240
mA
Operating current
IDD1*
One device bank; Active-Read-Precharge; BL = 4;
tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA; Address and control
inputs change once per clock cycle
1600
1480
mA
Percharge power-
down standby current
IDD2P**
All device banks are idle; Power-down mode; tCK = tCK(MIN);
CKE = LOW
360
mA
Idle standby current
IDD2F**
CS# = HIGH; All device banks are idle; tCK = tCK(MIN);
CKE = HIGH; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and DM
1000
920
mA
Active power-down
standby current
IDD3P**
One device bank active; Power-down mode; tCK = tCK(MIN);
CKE = LOW
840
760
mA
Active standby
current
IDD3N**
CS# = HIGH; CKE = HIGH; One device bank active;
tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM and DQS inputs change
twice per clock cycle; Address and other control inputs
changing once per clock cycle
1080
1000
mA
Operating current
IDD4R*
Burst = 2; Reads; Continuous burst; One device bank active;
Address and other control inputs changing once per clock
cycle; tCK = tCK(MIN); IOUT = 0mA
1640
1480
mA
Operating current
IDD4W*
Burst = 2; Writes; Continuous burst; One device bank active;
Address and other control inputs changing once per clock
cycle; tCK = tCK(MIN); DQ, DM and DQS inputs change twice per
clock cycle
1720
1400
mA
Auto refresh current
IDD5**
tRC = tRFC(MIN)
4920
4760
mA
Self refresh current
IDD6**
CKE < 0.2V
360
mA
Orerating current
IDD7*
Four device bank interleaving Reads Burst = 4 with auto
precharge; tRC = tRFC(MIN); tCK = tCK(MIN); Address and control
inputs change only during Active READ, or WRITE commands
3560
3120
mA
NOTE:
IDD specication is based on Micron components. Other DRAM Manufacturers specication may be different.
* Value calculated as one module rank in this operating condition and all other module ranks in IDD2P (CKE low) mode.
** Value calculated reects all module ranks in this operating condition.
AC OPERATING TEST CONDITIONS
Parameter/Condition
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage
VIH(AC)
VREF +0.31
V
Input Low (Logic 0) Voltage
VIL(AC)
VREF -0.31
V
Input Differential Voltage, CK and CK# inputs
VID(AC)
0.7
VCCQ+0.6
V
Input Crossing Point Voltage, CK and CK3 inputs
VIX(AC)
0.5*VCCQ-0.2
0.5*VCCQ+0.2
V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG265M64EFSU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG265M72EFSU262D4IM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU262D4IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU262D4IN | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU262D4ING | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
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