參數(shù)資料
型號: WV3HG2128M72AER403D6SG
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 9/12頁
文件大?。?/td> 259K
代理商: WV3HG2128M72AER403D6SG
WV3HG2128M72AER-D6
November 2006
Rev. 1
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Parameter
Symbol Condition
553
403
Units
Operating one
device bank active-
precharge current;
ICC0
tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
2,284
mA
Operating one device
bank active-read-
precharge current;
ICC1
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN
(ICC), tRCD = tRCD (ICC); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W.
2,554
mA
Precharge power-
down current;
ICC2P
All device banks idle; tCK = tCK (ICC); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING.
988
mA
Precharge quiet
standby current;
ICC2Q
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
1,780
mA
Precharge standby
current;
ICC2N
All device banks idle; tCK = tCK (ICC); CKE is HIGH, S# is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
1,960
mA
Active power-down
current;
ICC3P
All device banks open; tCK = tCK (ICC); CKE is LOW; Other
control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Fast PDN Exit
MR[12] = 0
1,780
mA
Slow PDN Exit
MR[12] = 1
1,132
mA
Active standby
current;
ICC3N
All device banks open; tCK = tCK(ICC), tRAS = tRAS MAX (ICC), tRP = tRP(ICC); CKE is
HIGH, S# is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
2,500
mA
Operating burst write
current;
ICC4W
All device banks open, Continuous burst writes; BL = 4, CL = CL (ICC), AL = 0; tCK =
tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
2,824
2,644
mA
Operating burst read
current;
ICC4R
All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (ICC), AL
= 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
2,914
2,734
mA
Burst refresh current;
ICC5
tCK = tCK (ICC); Refresh command at every tRFC (ICC) interval; CKE is HIGH, CS#
is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
5,740
mA
Self refresh current;
ICC6
CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING.
288
mA
Operating device
bank interleave read
current;
ICC7
All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (ICC), AL = tRCD (ICC)-1
x tCK (ICC); tCK = tCK (ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = tRCD(ICC); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are STABLE during
DESELECTs; Data bus inputs are SWITCHING; See ICC7 Conditions for detail.
4,804
mA
NOTE:
ICC specication is based on
SAMSUNG components. Other DRAM manufactures speicication may be different.
* Value calculated as on module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reects all module ranks in this operating condition.
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