參數(shù)資料
型號(hào): WV3HG232M72EER534D6MG
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 6/10頁
文件大小: 0K
代理商: WV3HG232M72EER534D6MG
WV3HG232M72EER-D6
June 2005
Rev. 1
ADVANCED
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DDR2 IDD SPECIFICATIONS AND CONDITIONS
Specications represent the total module power which includes DRAM, Registers, and PLL power.
Symbol
Rank 1
State
Proposed Conditions
665
534
403
Units
Rank 2
State
IDD0
Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,915
1,790
1,665
mA
IDD3N
IDD1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD),
tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are
SWITCHING; Data pattern is same as IDD4W
2,025
1,920
1,770
mA
IDD3N
IDD2P
Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
844
784
724
mA
IDD2P
IDD2Q
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus
inputsare STABLE; Data bus inputs are FLOATING
1,225
1,110
1,040
mA
IDD2F
IDD2N
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
1,165
1,090
1,060
mA
IDD2Q
IDD3P
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0mA
1,250
1,190
1,130
mA
IDD3P
Slow PDN Exit MRS(12) = 1mA
630
600
570
mA
IDD3N
Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
1,545
1,480
1,415
mA
IDD3N
IDD4W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
2,940
2,515
2,045
mA
IDD3N
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK
= tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
2,515
2,240
1,920
mA
IDD3N
IDD5B
Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
2,530
2,395
2,260
mA
IDD3N
IDD6
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
90
mA
IDD6
IDD7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =
tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same
as IDD4R; Refer to the following page for detailed timing conditions
3,935
3,605
3,365
mA
IDD3N
These specications are only valid for Samsung based modules
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