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參數(shù)資料
| 型號(hào)： | WV3HG32M40SEU534PD4ISG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 40 DDR DRAM MODULE, 0.5 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 178K |
| 代理商： | WV3HG32M40SEU534PD4ISG |
WV3HG32M40SEU-PD4
November 2006
Rev. 7
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
AC CHARACTERISTICS
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Command
and
Address
ACTIVE to ACTIVE (same bank) command
tRC
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
10
ns
ACTIVE to READ or WRITE delay
tRCD
15
ns
Four Bank Activate period
tFAW
50
ns
ACTIVE to PRECHARGE command
tRAS
45
70,000
45
70,000
40
70,000
ns
Internal READ to precharge command delay
tRTP
7.5
ns
Write recovery time
tWR
15
ns
Auto precharge write recovery + precharge time
tDAL
tWR + tRP
ns
Internal WRITE to READ command delay
tWTR
7.5
10
ns
PRECHARGE command period
tRP
15
ns
PRECHARGE ALL command period
tRPA
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
222
tCK
CKE low to CK,CK# uncertainty
tDELAY
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
ns
Self
Refresh
REFRESH to Active of Refresh to Refresh command
interval
tRFC
105
70,000
105
70,000
105
70,000
ns
Average periodic refresh interval
tREFI
7.8
μs
Exit self refresh to non-READ command
tXSNR
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
ns
Exit self refresh to READ command
tXSRD
200
tCK
Exit self refresh timing reference
tISXR
tIS
ps
ODT
ODT turn-on delay
tAOND
222222
tCK
ODT turn-on
tAON
tAC (MIN)
tAC (MAX)
+ 700
tAC (MIN)
tAC (MAX)
+ 1000
tAC (MIN)
tAC (MAX)
+ 1000
ps
ODT turn-off delay
tAOFD
2.5
tCK
ODT turn-off
tAOF
tAC (MIN)
tAC (MAX)
+ 600
tAC (MIN)
tAC (MAX)
+ 600
tAC (MIN)
tAC (MAX)
+ 600
ps
ODT turn-on (power-down mode)
tAONPD
tAC (MIN)
+ 2000
2 x tCK +
tAC (MAX)
+ 1000
tAC (MIN)
+ 2000
2 x tCK +
tAC (MAX)
+ 1000
tAC (MIN)
+ 2000
2 x tCK +
tAC (MAX)
+ 1000
ps
ODT turn-off (power-down mode)
tAOFPD
tAC (MIN)
+ 2000
2.5 x
tCK + tAC
(MAX) +
1000
tAC (MIN)
+ 2000
2.5 x
tCK + tAC
(MAX) +
1000
tAC (MIN)
+ 2000
2.5 x
tCK + tAC
(MAX) +
1000
ps
ODT to power-down entry latency
tANPD
333
tCK
ODT power-down exit latency
tAXPD
888
tCK
Power-Down
Exit active power-down to READ command,
MR[bit12=0]
tXARD
222
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7 - AL
6 - AL
tCK
A Exit precharge power-down to any non-READ
command.
tXP
222
tCK
CKE minimum high/low time
tCKE
333
tCK
Note:
AC specication is based on
ELPIDA components. Other DRAM manufactures specication may be different.
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