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參數(shù)資料
| 型號(hào)： | WV3HG32M72EEU534D4SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.5 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 173K |
| 代理商： | WV3HG32M72EEU534D4SG |
WV3HG32M72EEU-D4
January 2006
Rev. 0
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DDR2 ICC SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
Parameter
Active
Rank
State
Condition
806
665
553
403
Units
Operating one device
bank active-precharge
current;
ICC0
tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING.
TBD
1,245
1,200
1,155
mA
Operating one device
bank active-read-
precharge current;
ICC1
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK (ICC), tRC = tRC (ICC),
tRAS = tRAS MIN (ICC), tRCD = tRCD (ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data
pattern is same as ICC4W.
TBD
1,335
1,290
1,200
mA
Precharge power-down
current;
ICC2P
All device banks idle; tCK = tCK (ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
TBD
372
375
372
mA
Precharge quiet
standby current;
ICC2Q
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other
control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
TBD
570
525
mA
Precharge standby
current;
ICC2N
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
TBD
615
570
mA
Active power-down
current;
ICC3P
All device banks open; tCK = tCK (ICC); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING.
Fast PDN Exit
MR[12] = 0
TBD
615
570
mA
Slow PDN Exit
MR[12] = 1
TBD
435
mA
Active standby current;
ICC3N
All device banks open; tCK = tCK(ICC), tRAS = tRAS MAX (ICC), tRP = tRP(ICC);
CKE is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
975
930
885
mA
Operating burst write
current;
ICC4W
All device banks open, Continuous burst writes; BL = 4, CL = CL (ICC),
AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
TBD
2,190
1,875
1,515
mA
Operating burst read
current;
ICC4R
All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
= CL (ICC), AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
1,965
1,740
1,470
mA
Burst refresh current;
ICC5
tCK = tCK (ICC); Refresh command at every tRFC (ICC) interval; CKE
is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
1,830
1,785
1,740
mA
Self refresh current;
ICC6
CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING.
TBD
45
mA
Operating device bank
interleave read current;
ICC7
All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (ICC),
AL = tRCD (ICC)-1 x tCK (ICC); tCK = tCK (ICC), tRC = tRC(ICC), tRRD = tRRD(ICC),
tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs
are SWITCHING; See ICC7 Conditions for detail.
TBD
2,685
2,595
mA
Note:
ICC specication is based on SAMSUNG components. Other DRAM manufactures specication may be different.
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