參數(shù)資料
型號(hào)： WV3HG32M72EEU665PD4MG
廠(chǎng)商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類(lèi)： DRAM
英文描述： 32M X 72 DDR DRAM MODULE, 0.45 ns, DMA200
封裝： ROHS COMPLIANT, SO-DIMM-200
文件頁(yè)數(shù)： 11/14頁(yè)
文件大?。?/td> 208K
代理商： WV3HG32M72EEU665PD4MG
WV3HG32M72EEU-PD4
June 2006
Rev. 3
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 ICC SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
Symbol Proposed Conditions
806
665
553
403
Units
ICC0*
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1,245
1,200
1,155
mA
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
TBD
1,335
1,290
1,200
mA
ICC2P*
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
TBD
372
mA
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
TBD
570
525
mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
TBD
615
570
mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
TBD
615
570
mA
Slow PDN Exit MRS(12) = 1
TBD
435
mA
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
975
930
885
mA
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
2,190
1,875
1,515
mA
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC),
tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
TBD
1,965
1,740
1,470
mA
ICC5B**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
1,830
1,785
1,740
mA
ICC6**
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
TBD
45
mA
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
TBD
2,685
2,595
mA
Note: ICC specication is based on
SAMSUNG components. Other DRAM Manufacturers specication may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reects all module ranks in this operating condition.
相關(guān)PDF資料
PDF描述
WV3HG32M72EEU534PD4GG 32M X 72 DDR DRAM MODULE, 0.5 ns, DMA200
WV3HG32M72EEU665PD4ISG 32M X 72 DDR DRAM MODULE, 0.45 ns, DMA200
WV3HG32M72EEU534PD4IMG 32M X 72 DDR DRAM MODULE, 0.5 ns, DMA200
WV3HG64M32EEU403D4SG 64M X 32 DDR DRAM MODULE, 0.6 ns, ZMA200
WV3HG64M32EEU534D4SG 64M X 32 DDR DRAM MODULE, 0.5 ns, ZMA200
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
WV3HG64M32EEU403D4IMG 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 64Mx32 DDR2 SDRAM UNBUFFERED
WV3HG64M32EEU403D4ISG 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 64Mx32 DDR2 SDRAM UNBUFFERED
WV3HG64M32EEU403D4MG 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 64Mx32 DDR2 SDRAM UNBUFFERED
WV3HG64M32EEU403D4SG 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 64Mx32 DDR2 SDRAM UNBUFFERED
WV3HG64M32EEU534D4IMG 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 64Mx32 DDR2 SDRAM UNBUFFERED
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*