參數(shù)資料
型號: X1203S8I
英文描述: 30V Single N-Channel HEXFET Power MOSFET in a D-Pak package; Similar to IRFR3303 with Lead Free Packaging
中文描述: 實時時鐘
文件頁數(shù): 12/20頁
文件大?。?/td> 88K
代理商: X1203S8I
X1203
Characteristics subject to change without notice.
12 of 20
DEVICE ADDRESSING
Following a start condition, the master must output a
slave address byte. The first four bits of the slave
address byte specify access to the CCR. Slave bits
1101 access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to 111.
The last bit of the slave address byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 12.
After loading the entire slave address byte from the
SDA bus, the device compares the device identifier and
device select bits with 1101111. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following the slave byte is a two byte CCR address.
The CCR address is either supplied by the master
device or obtained from an internal counter.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is, for a random read of the clock/
control registers, the slave byte must be 1101111x in
both places.
Figure 12. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Slave Address Byte
Byte 0
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
Data Byte
Byte 3
A6
A5
0
0
0
0
0
0
0
1
1
0
1
1
1
R/W
1
Device Identifier
0
High Order Word Address
Byte 1 - X1202
Low Order Word Address
Byte 2 - X1202
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