參數(shù)資料
型號(hào): X1226V8T2
廠商: Intersil
文件頁(yè)數(shù): 4/25頁(yè)
文件大?。?/td> 0K
描述: IC RTC/CALENDAR/4K EE 8-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 帶卷 (TR)
12
FN8098.3
May 8, 2006
Figure 6. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1226 responds with
an acknowledge. After receiving both address bytes
the X1226 awaits the eight bits of data. After receiving
the 8 data bits, the X1226 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1226 then
begins an internal write cycle of the data to the nonvol-
atile memory. During the internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 7.
Figure 7. Byte Write Sequence
Figure 8. Writing 30 bytes to a 64-byte memory page starting at address 40.
Slave Address Byte
Byte 0
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
Data Byte
Byte 3
A6
A5
0
000
A8
0
1
0
1
0
1
0
1
R/W
1
Device Identifier
Array
CCR
0
Word Address 1
Byte 1
Word Address 0
Byte 2
S
t
a
r
t
S
t
o
p
Slave
Address
Word
Address 1
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals From
The Slave
Signals from
the Master
0
A
C
K
Word
Address 0
1
00 0 0 0 0 0
Address
40
23 Bytes
63
7 Bytes
Address
= 6
Address Pointer
Ends Here
Addr = 7
X1226
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