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參數(shù)資料
| 型號(hào)： | X1228S14-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大?。?/td> | 569K |
| 代理商： | X1228S14-2.7 |
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X1228
REV 1.3 3/24/04
Characteristics subject to change without notice.
23 of 31
www.xicor.com
Random Read
Random read operations allows the master to access
any location in the X1228. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt of
each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issu-
ing a stop condition. Refer to Figure 16 for the address,
acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 16. The X1228 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indi-
cating it requires additional data. The device continues
to output data for each acknowledge received. The mas-
ter terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to the start of the address space and the
X1228 continues to output data for each acknowledge
received. Refer to Figure 17 for the acknowledge and
data transfer sequence.
Figure 16. Random Address Read Sequence
Figure 17. Sequential Read Sequence
0
Slave
Address
Word
Address 1
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
A
C
K
Word
Address 0
1
1
1
1
1
1
1
1
0 0 0 0 0 0 0
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
相關(guān)PDF資料 |
PDF描述 |
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| X1228S14-2.7A | RTC Module With CPU Supervisor |
| X1228S14-2.7T1 | RTC Module With CPU Supervisor |
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| X1228S14I-2.7 | TVS Diode; Diode Type:Unidirectional TVS; Stand-Off Voltage, VRWM:12V; Breakdown Voltage, Vbr:13.3V; Capacitance, Cd:150pF; Package/Case:SOT-323; Breakdown Voltage Min:13.3V; Junction Capacitance:150pF; Leaded Process Compatible:No RoHS Compliant: No |
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