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參數(shù)資料
| 型號： | X1228S14-4.5A |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大?。?/td> | 569K |
| 代理商： | X1228S14-4.5A |
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X1228
REV 1.3 3/24/04
Characteristics subject to change without notice.
14 of 31
www.xicor.com
Table 4. Watchdog Timer Time-Out Options
INTERRUPT CONTROL AND FREQUENCY
OUTPUT REGISTER (INT)
Interrupt Control and Status Bits (IM, AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either the
AL1E and AL0E bits are set to ‘1’, respectively.
Two volatile bits (AL1 and AL0), associated with the two
alarms respectively, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the IRQ interrupt is enabled. The AL1 and AL0
bits in the status register are reset by the falling edge of
the eighth clock of a read of the register containing the
bits.
Pulse Interrupt Mode
The pulsed interrrupt mode allows for repetitive or
recurring alarm functionality. Hence an repetitive or
recurring alarm can be set for every n
th
second, or n
th
minute, or n
th
hour, or n
th
date, or for the same day of
the week. The pulsed interrupt mode can be consid-
ered a repetitive interrupt mode, with the repetition rate
set by the time setting of the alarm.
The Pulse Interrupt Mode is enabled when the IM bit is
set.
The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.
Programmable Frequency Output Bits—FO1, FO0
These are two output control bits. They select one of
three divisions of the internal oscillator, that is applied
to the PHZ output pin. Table 5 shows the selection bits
for this output. When using the PHZ output function,
the Alarm IRQ output function is disabled.
Table 5. Programmable Frequency Output Bits
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1 and
DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 6. Digital Trimming Registers
WD1 WD0
0
0
1
1
Watchdog Time-Out Period
0
1
0
1
1.75 seconds
750 milliseconds
250 milliseconds
Disabled (default)
IM Bit
0
Interrupt / Alarm Frequency
Single Time Event Set By Alarm
Repetitive / Recurring Time Event Set By
Alarm
1
FO1
0
0
1
1
FO0
0
1
0
1
Output Frequency
(average of 100 samples)
Alarm IRQ output
32.768kHz
4096Hz
1Hz
DTR Register
DTR2
DTR1
0
0
0
0
1
1
1
1
Estimated frequency
PPM
0 (Default)
+10
+20
+30
0
-10
-20
-30
DTR0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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