- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄9334 > X1288V14I-2.7 (Intersil)IC RTC/CAL/CPU SUP EE 14-TSSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | X1288V14I-2.7 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 13/27頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CAL/CPU SUP EE 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 95 |
| 類(lèi)型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線(xiàn)串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)
20
FN8102.3
April 14, 2006
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 14 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1288 resets itself without per-
forming the write. The contents of the array are not
affected.
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1288 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do
this, the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X1288 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X1288 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 16.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1288 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power-on reset
can download the entire contents of memory starting
at the first location.Upon receipt of the Slave Address
Byte with the R/W bit set to one, the X1288 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issu-
ing a stop condition. Refer to Figure 15 for the
address, acknowledge, and data transfer sequence.
Word
Address 0
S
t
a
r
t
S
t
o
p
Slave
Address
Word
Address 1
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
1
≤ n ≤ 128 for EEPROM array
1
≤ n ≤ 8 for CCR
1
10
FIGURE 14. PAGE WRITE SEQUENCE
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
FIGURE 15. CURRENT ADDRESS READ SEQUENCE
X1288
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-21M-MW | CONVERTER MOD DC/DC 10V 100W |
| X1288V14I | IC RTC/CAL/CPU SUP EE 14-TSSOP |
| VI-B1M-MW-B1 | CONVERTER MOD DC/DC 10V 100W |
| MCP4162T-503E/SN | IC POT DGTL SNGL 50K RHEO 8SOIC |
| MCP4161T-503E/SN | IC POT DGTL SNGL 50K SPI 8SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X1288V14I-4.5A | 功能描述:IC RTC/CAL/CPU SUP EE 14-TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 實(shí)時(shí)時(shí)鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:時(shí)鐘/日歷 特點(diǎn):警報(bào)器，閏年，SRAM 存儲(chǔ)容量:- 時(shí)間格式:HH:MM:SS（12/24 小時(shí)） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
| X1288V14I-4.5AT1 | 功能描述:IC RTC/CAL/CPU SUP EE 14-TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 實(shí)時(shí)時(shí)鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:時(shí)鐘/日歷 特點(diǎn):警報(bào)器，閏年，SRAM 存儲(chǔ)容量:- 時(shí)間格式:HH:MM:SS（12/24 小時(shí)） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
| X1288V14IT1 | 功能描述:IC RTC/CAL/CPU SUP EE 14-TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 實(shí)時(shí)時(shí)鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:時(shí)鐘/日歷 特點(diǎn):警報(bào)器，閏年，SRAM 存儲(chǔ)容量:- 時(shí)間格式:HH:MM:SS（12/24 小時(shí)） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
| X1288V14IZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| X1288V14IZ-2.7 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:2-Wire⑩ RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。