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參數(shù)資料
| 型號： | X20C04E-25 |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT02; Number of Contacts:2; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle |
| 中文描述： | 非易失性靜態(tài)RAM |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 67K |
| 代理商： | X20C04E-25 |
X20C04
3
Power-Up Recall
Upon power-up (V
CC
), the X20C04 performs an auto-
matic array recall. When V
CC
minimum is reached, the
recall is initiated, regardless of the state of
CE
,
OE
,
WE
and
NE
.
Write Protection
The X20C04 has five write protect features that are
employed to protect the contents of both the nonvolatile
memory and the RAM.
V
CC
Sense—All functions are inhibited when V
CC
is
≤
3.5V.
A RAM write is required before a Store Cycle is
initiated.
Write Inhibit—Holding either
OE
LOW,
WE
HIGH,
CE
HIGH, or
NE
HIGH during power-up and power-
down will prevent an inadvertent store operation.
Noise Protection—A combined
WE
,
NE
,
OE
and
CE
pulse of less than 20ns will not initiate a Store
Cycle.
Noise Protection—A combined
WE
,
NE
,
OE
and
CE
pulse of less than 20ns will not initiate a recall
cycle.
DEVICE OPERATION
The
CE
,
OE
,
WE
and
NE
inputs control the X20C04
operation. The X20C04 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either
OE
or
CE
is HIGH, or
when
NE
is LOW.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE
and
OE
to be LOW with
WE
and
NE
HIGH. A write
operation requires
CE
and
WE
to be LOW with
NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the X20C04.
Nonvolatile Operations
With
NE
LOW, recall operation is performed in the same
manner as RAM read operation. A recall operation
causes the entire contents of the E
2
PROM to be written
into the RAM array. The time required for the operation
to complete is 5
μ
s or less. A store operation causes the
entire contents of the RAM array to be stored in the
nonvolatile E
2
PROM. The time for the operation to
complete is 5ms or less.
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X20C04DMB-15 | Nonvolatile Static RAM |
| X20C04DMB-20 | Nonvolatile Static RAM |
| X20C04DMB-25 | Nonvolatile Static RAM |
| X20C04E | Nonvolatile Static RAM |
| X20C04EI-15 | Nonvolatile Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X20C04EI | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Nonvolatile Static RAM |
| X20C04EI-15 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Nonvolatile Static RAM |
| X20C04EI-20 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Nonvolatile Static RAM |
| X20C04EI-25 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Nonvolatile Static RAM |
| X20C04EM | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Nonvolatile Static RAM |
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