參數(shù)資料
型號(hào): X24022P-3
英文描述: CONNECTOR HARDWARE: MALE SCREWLOCKS
中文描述: 串行E2PROM
文件頁(yè)數(shù): 10/14頁(yè)
文件大?。?/td> 58K
代理商: X24022P-3
10
X24022
Notes:
(4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tLOW
tSU:STO
tR
tBUF
SCL
SDA IN
SDA OUT
tDH
tAA
tF
tHIGH
3848 FHD F04
Bus Timing
POWER-UP TIMING
Symbol
Parameter
Max.
Units
t
PUR(4)
t
PUW(4)
Power-Up to Read Operation
Power-Up to Write Operation
1
5
ms
ms
3848 PGM T09
Read & Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
f
SCL
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0
100
100
3.5
KHz
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
ns
3848 PGM T08
0.3
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
300
A.C. CHARACTERISTICS LIMITS
(Over recommended operating conditions unless otherwise specified)
A.C. CONDITIONS OF TEST
Input Pulse Levels
V
CC
x 0.1 to V
CC
x 0.9
Input Rise and
Fall Times
Input and Output
Timing Levels
10 ns
V
CC
x 0.5
3848 PGM T02
EQUIVALENT A.C. LOAD CIRCUIT
5.0V
1533
100pF
Output
3848 FHD F18
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