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參數(shù)資料
| 型號(hào)： | X24022SI |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Isolated Flyback Switching Regulator with 9V Output |
| 中文描述： | 隔離反激式開關(guān)穩(wěn)壓9V輸出 |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 58K |
| 代理商： | X24022SI |
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X24022
5
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24022
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
DATA
Figure 4. Slave Address
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see Figure 4). For the X24022 this is fixed as 1010[B].
The next three significant bits address a particular
device. A system could have up to eight X24022 devices
on the bus (see Figure 10). The eight addresses are
defined by the state of the A
0
, A
1
and A
2
inputs.
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the X24022 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of A
0
,
A
1
and A
2
inputs). Upon a correct compare the X24022
outputs an acknowledge on the SDA line. Depending on
the state of the R/
W
bit, the X24022 will execute a read
or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24022 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 256 words of memory. Upon receipt of the word
address the X24022 responds with an acknowledge,
and awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
X24022 begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
X24022 inputs are disabled, and the device will not
respond to any requests from the master. Refer to
Figure 5 for the address, acknowledge and data transfer
sequence.
3848 FHD F09
Figure 5. Byte Write
3848 FHD F10
1
0
1
0
A2
A1
A0
R/W
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24022SM | Serial E2PROM |
| X24022 | Controller IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes |
| X24022P | Controller IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes |
| X24022P-2.7 | Jack Screw; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
| X24022P-3 | CONNECTOR HARDWARE: MALE SCREWLOCKS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24022SI-2.7 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24022SI-3 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24022SM | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24022SM-2.7 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24022SM-3 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
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