9800-5004.1 1/31/00 EP
Xicor, 2000 Patents Pending
Characteristics subject to change without notice.
1 of 18
FUNCTIONAL DIAGRAM
SERIAL E
2
PROM DATA
AND ADDRESS (SDA)
SCL
S1
S0
WP
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE PROTECT
CONTROL LOGIC
DEVICE
SELECT
LOGIC
PAGE
DECODE
LOGIC
DATA REGISTER
Y DECODE LOGIC
WRITE VOLTAGE
CONTROL
SERIAL E
2
PROM
ARRAY
32K x 8
Preliminary
X24256
400KHz 2-Wire Serial E
2
PROM
256K
32K x 8 Bit
FEATURES
400KHz 2-Wire Serial Interface
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power
Supply Versions
64 Byte Page Write Mode
—Minimizes Total Write Time Per Word
Internally Organized 32K x 8
Bidirectional Data Transfer Protocol
Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
8-Lead XBGA
8-Lead SOIC
14-Lead TSSOP
μ
A
DESCRIPTION
The X24256 is a CMOS Serial E
organized 32K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
2
PROM, internally
Two device select inputs (S
devices to share a common two wire bus.
0
–S
1
) allow up to four
These pins have internal pull downs, so they are read
as LOW if not connected.
A WP pin, when pulled HIGH prevents any nonvolatile
writes to the array. When not connected WP is pulled
LOW, so the device is not normally protected.
Xicor E
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
2
PROMs are designed and tested for applica-
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